/*!
 * @file    	apm32f10x.h
 * @brief	 	CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
 *
 * @details		This file contains all the peripheral register's definitions, bits definitions and memory mapping
 *
 * @version		V1.0.0
 * @author  	
 * @date    	2019-12-17
 *
 */

#ifndef __APM32F10x_H
#define __APM32F10x_H

#ifdef __cplusplus
 extern "C" {
#endif 
  
/*!
 *	APM32F10X_LD: APM32 Low density devices
 *	APM32F10X_MD: APM32 Medium density devices
 *  APM32F10X_HD: APM32 High density devices
 */
#if !defined (APM32F10X_LD)  && !defined (APM32F10X_MD) && !defined (APM32F10X_HD)
#error "Please select a the target APM32F10x device used in your application (in apm32f10x.h file)"
#endif

/**
 * @brief Define Value of the External oscillator in Hz
  */           
#ifndef  HXT_VALUE 
 #define HXT_VALUE				((uint32_t)8000000)
#endif

/** Time out for HXT start up */
#define HXT_STARTUP_TIMEOUT		((uint16_t)0x0500)

/** Value of the Internal oscillator in Hz */
#define HIRC_VALUE    			((uint32_t)8000000)

/**
 * @brief APM32F10x Standard Peripheral Library version number
   */
#define __APM32F10X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
#define __APM32F10X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
#define __APM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
#define __APM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
#define __APM32F10X_STDPERIPH_VERSION       ( (__APM32F10X_STDPERIPH_VERSION_MAIN << 24)\
                                             |(__APM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
                                             |(__APM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
                                             |(__APM32F10X_STDPERIPH_VERSION_RC))


/** APM32 devices does not provide an MPU */
 #define __MPU_PRESENT				0
/** APM32 uses 4 Bits for the Priority Levels  */
#define __NVIC_PRIO_BITS          	4
/** Set to 1 if different SysTick Config is used */
#define __Vendor_SysTickConfig    	0

/**
 * @brief APM32F10x Interrupt Number Definition, according to the selected device 
 *        in @ref Library_configuration_section 
 */
typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */

/******  APM32 specific Interrupt Numbers *********************************************************/
  WWDT_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
  PVD_IRQn                    = 1,      /*!< PVD through EINT Line detection Interrupt            */
  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
  FMC_IRQn                    = 4,      /*!< FMC global Interrupt                               */
  RCM_IRQn                    = 5,      /*!< RCM global Interrupt                                 */
  EINT0_IRQn                  = 6,      /*!< EINT Line0 Interrupt                                 */
  EINT1_IRQn                  = 7,      /*!< EINT Line1 Interrupt                                 */
  EINT2_IRQn                  = 8,      /*!< EINT Line2 Interrupt                                 */
  EINT3_IRQn                  = 9,      /*!< EINT Line3 Interrupt                                 */
  EINT4_IRQn                  = 10,     /*!< EINT Line4 Interrupt                                 */
  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */

#ifdef APM32F10X_LD
  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
  EINT9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
  TMR1_BRK_IRQn               = 24,     /*!< TMR1 Break Interrupt                                 */
  TMR1_UP_IRQn                = 25,     /*!< TMR1 Update Interrupt                                */
  TMR1_TRG_COM_IRQn           = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
  TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
  TMR2_IRQn                   = 28,     /*!< TMR2 global Interrupt                                */
  TMR3_IRQn                   = 29,     /*!< TMR3 global Interrupt                                */
  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
  EINT15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EINT Line Interrupt                */
  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EINT Line Interrupt */    
  FPU_IRQn					  = 43,		/*!< FPU Global Interrupt 								  */ 
  QSPI_IRQn					  = 44,		/*!< QSPI Global Interrupt 								  */
#endif /* APM32F10X_LD */  


#ifdef APM32F10X_MD
  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
  EINT9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
  TMR1_BRK_IRQn               = 24,     /*!< TMR1 Break Interrupt                                 */
  TMR1_UP_IRQn                = 25,     /*!< TMR1 Update Interrupt                                */
  TMR1_TRG_COM_IRQn           = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
  TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
  TMR2_IRQn                   = 28,     /*!< TMR2 global Interrupt                                */
  TMR3_IRQn                   = 29,     /*!< TMR3 global Interrupt                                */
  TMR4_IRQn                   = 30,     /*!< TMR4 global Interrupt                                */
  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
  EINT15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EINT Line Interrupt                */
  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EINT Line Interrupt */  
  FPU_IRQn					  = 43,		/*!< FPU Global Interrupt 								  */   
  QSPI_IRQn					  = 44,		/*!< QSPI Global Interrupt 								  */
#endif /* APM32F10X_MD */  

#ifdef APM32F10X_HD
  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
  EINT9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
  TMR1_BRK_IRQn               = 24,     /*!< TMR1 Break Interrupt                                 */
  TMR1_UP_IRQn                = 25,     /*!< TMR1 Update Interrupt                                */
  TMR1_TRG_COM_IRQn           = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
  TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
  TMR2_IRQn                   = 28,     /*!< TMR2 global Interrupt                                */
  TMR3_IRQn                   = 29,     /*!< TMR3 global Interrupt                                */
  TMR4_IRQn                   = 30,     /*!< TMR4 global Interrupt                                */
  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
  EINT15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EINT Line Interrupt                */
  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EINT Line Interrupt */
  TMR8_BRK_IRQn               = 43,     /*!< TMR8 Break Interrupt                                 */
  TMR8_UP_IRQn                = 44,     /*!< TMR8 Update Interrupt                                */
  TMR8_TRG_COM_IRQn           = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
  TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
  TMR5_IRQn                   = 50,     /*!< TMR5 global Interrupt                                */
  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
  TMR6_IRQn                   = 54,     /*!< TMR6 global Interrupt                                */
  TMR7_IRQn                   = 55,     /*!< TMR7 global Interrupt                                */
  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
#endif /* APM32F10X_HD */       
} IRQn_Type;

/**
  * @}
  */

#include "core_cm3.h"
#include "system_apm32f10x.h"
#include <stdint.h>


typedef int32_t  s32;
typedef int16_t s16;
typedef int8_t  s8;

typedef const int32_t sc32;
typedef const int16_t sc16;
typedef const int8_t sc8;

typedef __IO int32_t  vs32;
typedef __IO int16_t  vs16;
typedef __IO int8_t   vs8;

typedef __I int32_t vsc32;
typedef __I int16_t vsc16;
typedef __I int8_t vsc8;

typedef uint32_t  u32;
typedef uint16_t u16;
typedef uint8_t  u8;

typedef const uint32_t uc32;
typedef const uint16_t uc16;
typedef const uint8_t uc8; 

typedef __IO uint32_t  vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t  vu8;

typedef __I uint32_t vuc32;
typedef __I uint16_t vuc16;
typedef __I uint8_t vuc8;

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif

enum {BIT_RESET, BIT_SET};
enum {RESET, SET};
enum {DISABLE, ENABLE};
enum {ERROR, SUCCESS};

#ifndef NULL 
#define NULL	((void *)0)
#endif

#if defined (__CC_ARM )
#pragma anon_unions
#endif

/** @addtogroup Device_Peripheral_peripherals
  * @{
  */

/**
  * @brief CRC calculation unit (CRC)
  */

typedef struct {                                /*!< (@ 0x40023000) CRC Structure                                              */
 
  union {
    __IOM uint32_t DATA;                        /*!< (@ 0x00000000) Data register                                              */
    
    struct {
      __IOM uint32_t DATA       : 32;           /*!< [31..0] Data Register                                                     */
    } DATA_B;
  } ;
  
  union {
    __IOM uint32_t DB;                          /*!< (@ 0x00000004) Independent Data register                                  */
    
    struct {
      __IOM uint32_t DB         : 8;            /*!< [7..0] Independent Data register                                          */
    } DB_B;
  } ;
  
  union {
    __OM  uint32_t CTRL;                        /*!< (@ 0x00000008) Control register                                           */
    
    struct {
      __OM  uint32_t RST        : 1;            /*!< [0..0] Reset bit                                                          */
    } CTRL_B;
  } ;
} CRC_T;                                     /*!< Size = 12 (0xc)                                                           */

/**
  * @brief Flash memory controller (FMC)
  */

typedef struct {                                /*!< (@ 0x40022000) FMC Structure                                              */
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000000) Flash access control register                              */
    
    struct {
      __IOM uint32_t LATENCY    : 3;            /*!< [2..0] Latency                                                            */
      __IOM uint32_t HCAEN      : 1;            /*!< [3..3] Flash half cycle access enable                                     */
      __IOM uint32_t PBEN       : 1;            /*!< [4..4] Prefetch buffer enable                                             */
      __IM  uint32_t PBSF       : 1;            /*!< [5..5] Prefetch buffer status                                             */
    } CTRL1_B;
  } ;
  
  union {
    __OM  uint32_t KEY;                         /*!< (@ 0x00000004) key register                                               */
    
    struct {
      __OM  uint32_t KEY        : 32;           /*!< [31..0] FPEC key                                                          */
    } KEY_B;
  } ;
  
  union {
    __OM  uint32_t OBKEY;                       /*!< (@ 0x00000008) option byte key register                                   */
    
    struct {
      __OM  uint32_t KEY        : 32;           /*!< [31..0] Option byte key                                                   */
    } OBKEY_B;
  } ;
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x0000000C) status register                                            */
    
    struct {
      __IM  uint32_t BUSYF      : 1;            /*!< [0..0] Busy                                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t PEF        : 1;            /*!< [2..2] Programming error                                                  */
      __IM  uint32_t            : 1;
      __IOM uint32_t WPEF       : 1;            /*!< [4..4] Write protection error                                             */
      __IOM uint32_t OCF        : 1;            /*!< [5..5] End of operation                                                   */
    } STS_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000010) Control register                                           */
    
    struct {
      __IOM uint32_t PG         : 1;            /*!< [0..0] Programming                                                        */
      __IOM uint32_t PAGEERA    : 1;            /*!< [1..1] Page Erase                                                         */
      __IOM uint32_t MASSERA    : 1;            /*!< [2..2] Mass Erase                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t OBP        : 1;            /*!< [4..4] Option byte programming                                            */
      __IOM uint32_t OBE        : 1;            /*!< [5..5] Option byte erase                                                  */
      __IOM uint32_t STA        : 1;            /*!< [6..6] Start                                                              */
      __IOM uint32_t LOCK       : 1;            /*!< [7..7] Lock                                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t OBWEN      : 1;            /*!< [9..9] Option bytes write enable                                          */
      __IOM uint32_t ERRIE      : 1;            /*!< [10..10] Error interrupt enable                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t OCIE       : 1;            /*!< [12..12] End of operation interrupt enable                                */
    } CTRL2_B;
  } ;
  
  union {
    __OM  uint32_t ADD;                         /*!< (@ 0x00000014) Flash address register                                     */
    
    struct {
      __OM  uint32_t ADD        : 32;           /*!< [31..0] Flash Address                                                     */
    } ADD_B;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IM  uint32_t OBCS;                          /*!< (@ 0x0000001C) Option byte register                                       */
    
    struct {
      __IM  uint32_t OBE        : 1;            /*!< [0..0] Option byte error                                                  */
      __IM  uint32_t READPORT   : 1;            /*!< [1..1] Read protection                                                    */
      __IM  uint32_t WDT        : 1;            /*!< [2..2] WDG_SW                                                             */
      __IM  uint32_t STOPRST    : 1;            /*!< [3..3] nRST_STOP                                                          */
      __IM  uint32_t STDBYRST   : 1;            /*!< [4..4] nRST_STDBY                                                         */
      __IM  uint32_t NOTUSED    : 8;            /*!< [12..5] NOTUSED                                                           */
      __IM  uint32_t DATA0      : 8;            /*!< [20..13] Data0                                                            */
      __IM  uint32_t DATA1      : 8;            /*!< [28..21] Data1                                                            */
    } OBCS_B;
  } ;
  
  union {
    __IM  uint32_t WRTPORT;                          /*!< (@ 0x00000020) Write protection register                                  */
    
    struct {
      __IM  uint32_t WRTPORT    : 32;           /*!< [31..0] Write protect                                                     */
    } WRTPORT_B;
  } ;
} FMC_T;                                     /*!< Size = 36 (0x24)                                                          */

/**
  * @brief Reset and clock management unit (RCM)
  */

typedef struct {                                /*!< (@ 0x40021000) RCM Structure                                              */
  
  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Clock control register (RCM_CTRL)                          */
    
    struct {
      __IOM uint32_t HIRCEN     : 1;            /*!< [0..0] Internal High Speed clock enable                                   */
      __IM  uint32_t HIRCRDYF   : 1;            /*!< [1..1] Internal High Speed clock ready flag                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t HIRCTRIM   : 5;            /*!< [7..3] Internal High Speed clock trimming                                 */
      __IM  uint32_t HIRCCAL    : 8;            /*!< [15..8] Internal High Speed clock Calibration                             */
      __IOM uint32_t HXTEN      : 1;            /*!< [16..16] External High Speed clock enable                                 */
      __IM  uint32_t HXTRDYF    : 1;            /*!< [17..17] External High Speed clock ready flag                             */
      __IOM uint32_t HXTBYP     : 1;            /*!< [18..18] External High Speed clock Bypass                                 */
      __IOM uint32_t CSSEN      : 1;            /*!< [19..19] Clock Security System enable                                     */
      __IM  uint32_t            : 4;
      __IOM uint32_t PLLEN      : 1;            /*!< [24..24] PLL enable                                                       */
      __IM  uint32_t PLLRDYF    : 1;            /*!< [25..25] PLL clock ready flag                                             */
    } CTRL_B;
  } ;
  
  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000004) Clock configuration register (RCM_CFGR)                    */
    
    struct {
      __IOM uint32_t SCSEL      : 2;            /*!< [1..0] System clock Switch                                                */
      __IM  uint32_t SCS        : 2;            /*!< [3..2] System Clock Switch Status                                         */
      __IOM uint32_t AHBDIV     : 4;            /*!< [7..4] AHB prescaler                                                      */
      __IOM uint32_t APB1DIV    : 3;            /*!< [10..8] APB Low speed prescaler (APB1)                                    */
      __IOM uint32_t APB2DIV    : 3;            /*!< [13..11] APB High speed prescaler (APB2)                                  */
      __IOM uint32_t ADCDIV     : 2;            /*!< [15..14] ADC prescaler                                                    */
      __IOM uint32_t PLLSEL     : 1;            /*!< [16..16] PLL entry clock source                                           */
      __IOM uint32_t PLLXTDIV   : 1;            /*!< [17..17] HSE divider for PLL entry                                        */
      __IOM uint32_t PLLMF      : 4;            /*!< [21..18] PLL Multiplication Factor                                        */
      __IOM uint32_t USBDIV     : 1;            /*!< [22..22] USB OTG FS prescaler                                             */
      __IM  uint32_t            : 1;
      __IOM uint32_t COC        : 3;            /*!< [26..24] Microcontroller clock output                                     */
      __IOM uint32_t FPUDIV     : 1;            /*!< [27..27] FPUDIV                                                           */
    } CFG_B;
  } ;
  
  union {
    __IOM uint32_t INT;                         /*!< (@ 0x00000008) Clock interrupt control register (RCM_INT)                 */
    
    struct {
      __IM  uint32_t LIRCRDYIF  : 1;            /*!< [0..0] LIR Ready Interrupt flag                                           */
      __IM  uint32_t LXTRDYIF   : 1;            /*!< [1..1] LXT Ready Interrupt flag                                           */
      __IM  uint32_t HIRCRDYIF  : 1;            /*!< [2..2] HIR Ready Interrupt flag                                           */
      __IM  uint32_t HXTRDYIF   : 1;            /*!< [3..3] HXT Ready Interrupt flag                                           */
      __IM  uint32_t PLLRDYIF   : 1;            /*!< [4..4] PLL Ready Interrupt flag                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t CSSIF      : 1;            /*!< [7..7] Clock Security System Interrupt flag                               */
      __IOM uint32_t LIRCRDYIE  : 1;            /*!< [8..8] LIR Ready Interrupt Enable                                         */
      __IOM uint32_t LXTRDYIE   : 1;            /*!< [9..9] LXT Ready Interrupt Enable                                         */
      __IOM uint32_t HIRCRDYIE  : 1;            /*!< [10..10] HIR Ready Interrupt Enable                                       */
      __IOM uint32_t HXTRDYIE   : 1;            /*!< [11..11] HXT Ready Interrupt Enable                                       */
      __IOM uint32_t PLLRDYIE   : 1;            /*!< [12..12] PLL Ready Interrupt Enable                                       */
      __IM  uint32_t            : 3;
      __OM  uint32_t LIRCRDYC   : 1;            /*!< [16..16] LIR Ready Interrupt Clear                                        */
      __OM  uint32_t LXTRDYC    : 1;            /*!< [17..17] LXT Ready Interrupt Clear                                        */
      __OM  uint32_t HIRCRDYC   : 1;            /*!< [18..18] HIR Ready Interrupt Clear                                        */
      __OM  uint32_t HXTRDYC    : 1;            /*!< [19..19] HXT Ready Interrupt Clear                                        */
      __OM  uint32_t PLLRDYC    : 1;            /*!< [20..20] PLL Ready Interrupt Clear                                        */
      __IM  uint32_t            : 2;
      __OM  uint32_t CSSIFC     : 1;            /*!< [23..23] Clock security system interrupt clear                            */
    } INT_B;
  } ;
  
  union {
    __IOM uint32_t APB2RST;                     /*!< (@ 0x0000000C) APB2 peripheral reset register (RCM_APB2RST)               */
    
    struct {
      __IOM uint32_t AFIORST    : 1;            /*!< [0..0] Alternate function I/O reset                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t PARST      : 1;            /*!< [2..2] IO port A reset                                                    */
      __IOM uint32_t PBRST      : 1;            /*!< [3..3] IO port B reset                                                    */
      __IOM uint32_t PCRST      : 1;            /*!< [4..4] IO port C reset                                                    */
      __IOM uint32_t PDRST      : 1;            /*!< [5..5] IO port D reset                                                    */
      __IOM uint32_t PERST      : 1;            /*!< [6..6] IO port E reset                                                    */
      __IOM uint32_t PFRST      : 1;            /*!< [7..7] IO port F reset                                                    */
      __IOM uint32_t PGRST      : 1;            /*!< [8..8] IO port G reset                                                    */
      __IOM uint32_t ADC1RST    : 1;            /*!< [9..9] ADC 1 interface reset                                              */
      __IOM uint32_t ADC2RST    : 1;            /*!< [10..10] ADC 2 interface reset                                            */
      __IOM uint32_t TMR1RST    : 1;            /*!< [11..11] TMR1 timer reset                                                 */
      __IOM uint32_t SPI1RST    : 1;            /*!< [12..12] SPI 1 reset                                                      */
      __IOM uint32_t TMR8RST    : 1;            /*!< [13..13] TMR8 timer reset                                                 */
      __IOM uint32_t USART1RST  : 1;            /*!< [14..14] USART1 reset                                                     */
      __IOM uint32_t ADC3RST    : 1;            /*!< [15..15] ADC 3 interface reset                                            */
    } APB2RST_B;
  } ;
  
  union {
    __IOM uint32_t APB1RST;                     /*!< (@ 0x00000010) APB1 peripheral reset register (RCM_APB1RST)               */
    
    struct {
      __IOM uint32_t TMR2RST    : 1;            /*!< [0..0] Timer 2 reset                                                      */
      __IOM uint32_t TMR3RST    : 1;            /*!< [1..1] Timer 3 reset                                                      */
      __IOM uint32_t TMR4RST    : 1;            /*!< [2..2] Timer 4 reset                                                      */
      __IOM uint32_t TMR5RST    : 1;            /*!< [3..3] Timer 5 reset                                                      */
      __IOM uint32_t TMR6RST    : 1;            /*!< [4..4] Timer 6 reset                                                      */
      __IOM uint32_t TMR7RST    : 1;            /*!< [5..5] Timer 7 reset                                                      */
      __IM  uint32_t            : 5;
      __IOM uint32_t WWDTRST    : 1;            /*!< [11..11] Window watchdog reset                                            */
      __IM  uint32_t            : 2;
      __IOM uint32_t SPI2RST    : 1;            /*!< [14..14] SPI2 reset                                                       */
      __IOM uint32_t SPI3RST    : 1;            /*!< [15..15] SPI3 reset                                                       */
      __IOM uint32_t USART2RST  : 1;            /*!< [16..16] USART 2 reset                                                    */
      __IOM uint32_t USART3RST  : 1;            /*!< [17..17] USART 3 reset                                                    */
      __IOM uint32_t UART4RST   : 1;            /*!< [18..18] UART 4 reset                                                     */
      __IOM uint32_t UART5RST   : 1;            /*!< [19..19] UART 5 reset                                                     */
      __IOM uint32_t I2C1RST    : 1;            /*!< [20..20] I2C1 reset                                                       */
      __IOM uint32_t I2C2RST    : 1;            /*!< [21..21] I2C2 reset                                                       */
      __IOM uint32_t USBRST     : 1;            /*!< [22..22] USB reset                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t CANRST     : 1;            /*!< [24..24] CAN reset                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t BAKRRST     : 1;            /*!< [26..26] Bakr interface reset                                           */
      __IOM uint32_t PMURST     : 1;            /*!< [27..27] Power interface reset                                            */
      __IOM uint32_t DACRST     : 1;            /*!< [28..28] DAC interface reset                                              */
    } APB1RST_B;
  } ;
  
  union {
    __IOM uint32_t AHBCLKEN;                    /*!< (@ 0x00000014) AHB clock enable register (RCM_AHBCLKEN)                   */
    
    struct {
      __IOM uint32_t DMA1CLKE   : 1;            /*!< [0..0] DMA1 clock enable                                                  */
      __IOM uint32_t DMA2CLKE   : 1;            /*!< [1..1] DMA2 clock enable                                                  */
      __IOM uint32_t SRAMCLKE   : 1;            /*!< [2..2] SRAM interface clock enable                                        */
      __IOM uint32_t FPUCLKE    : 1;            /*!< [3..3] FLITF clock enable                                                 */
      __IOM uint32_t FMCCLKE    : 1;            /*!< [4..4] CRC clock enable                                                   */
      __IOM uint32_t QSPICLKE   : 1;            /*!< [5..5] QSPICLKE                                                           */
      __IOM uint32_t CRCCLKE    : 1;            /*!< [6..6] CRCCLKE                                                            */
      __IM  uint32_t            : 1;
      __IOM uint32_t EMMCCLKEN  : 1;            /*!< [8..8] FSMC clock enable                                                  */
      __IM  uint32_t            : 1;
      __IOM uint32_t SDIOCLKE   : 1;            /*!< [10..10] SDIO clock enable                                                */
    } AHBCLKEN_B;
  } ;
  
  union {
    __IOM uint32_t APB2CLKEN;                   /*!< (@ 0x00000018) APB2 clock enable register (RCM_APB2CLKEN)                 */
    
    struct {
      __IOM uint32_t AFIOCLKE   : 1;            /*!< [0..0] Alternate function I/O clock enable                                */
      __IM  uint32_t            : 1;
      __IOM uint32_t PACLKE     : 1;            /*!< [2..2] I/O port A clock enable                                            */
      __IOM uint32_t PBCLKE     : 1;            /*!< [3..3] I/O port B clock enable                                            */
      __IOM uint32_t PCCLKE     : 1;            /*!< [4..4] I/O port C clock enable                                            */
      __IOM uint32_t PDCLKE     : 1;            /*!< [5..5] I/O port D clock enable                                            */
      __IOM uint32_t PECLKE     : 1;            /*!< [6..6] I/O port E clock enable                                            */
      __IOM uint32_t PFCLKE     : 1;            /*!< [7..7] I/O port F clock enable                                            */
      __IOM uint32_t PGCLKE     : 1;            /*!< [8..8] I/O port G clock enable                                            */
      __IOM uint32_t ADC1CLKE   : 1;            /*!< [9..9] ADC 1 interface clock enable                                       */
      __IOM uint32_t ADC2CLKE   : 1;            /*!< [10..10] ADC 2 interface clock enable                                     */
      __IOM uint32_t TMR1CLKE   : 1;            /*!< [11..11] TMR1 Timer clock enable                                          */
      __IOM uint32_t SPI1CLKE   : 1;            /*!< [12..12] SPI 1 clock enable                                               */
      __IOM uint32_t TMR8CLKE   : 1;            /*!< [13..13] TMR8 Timer clock enable                                          */
      __IOM uint32_t USART1CLKE : 1;            /*!< [14..14] USART1 clock enable                                              */
      __IOM uint32_t ADC3CLKE   : 1;            /*!< [15..15] ADC3 interface clock enable                                      */
    } APB2CLKEN_B;
  } ;
  
  union {
    __IOM uint32_t APB1CLKEN;                   /*!< (@ 0x0000001C) APB1 clock enable register (RCM_APB1CLKEN)                 */
    
    struct {
      __IOM uint32_t TMR2CLKE   : 1;            /*!< [0..0] Timer 2 clock enable                                               */
      __IOM uint32_t TMR3CLKE   : 1;            /*!< [1..1] Timer 3 clock enable                                               */
      __IOM uint32_t TMR4CLKE   : 1;            /*!< [2..2] Timer 4 clock enable                                               */
      __IOM uint32_t TMR5CLKE   : 1;            /*!< [3..3] Timer 5 clock enable                                               */
      __IOM uint32_t TMR6CLKE   : 1;            /*!< [4..4] Timer 6 clock enable                                               */
      __IOM uint32_t TMR7CLKE   : 1;            /*!< [5..5] Timer 7 clock enable                                               */
      __IM  uint32_t            : 5;
      __IOM uint32_t WWDTCLKE   : 1;            /*!< [11..11] Window watchdog clock enable                                     */
      __IM  uint32_t            : 2;
      __IOM uint32_t SPI2CLKE   : 1;            /*!< [14..14] SPI 2 clock enable                                               */
      __IOM uint32_t SPI3CLKE   : 1;            /*!< [15..15] SPI 3 clock enable                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t USART2CLKE : 1;            /*!< [17..17] USART 2 clock enable                                             */
      __IOM uint32_t USART3CLKE : 1;            /*!< [18..18] USART 3 clock enable                                             */
      __IOM uint32_t UART4CLKE  : 1;            /*!< [19..19] UART 4 clock enable                                              */
      __IOM uint32_t UART5CLKE  : 1;            /*!< [20..20] UART 5 clock enable                                              */
      __IOM uint32_t I2C1CLKE   : 1;            /*!< [21..21] I2C 1 clock enable                                               */
      __IOM uint32_t I2C2CLKE   : 1;            /*!< [22..22] I2C 2 clock enable                                               */
      __IOM uint32_t USBCLKE    : 1;            /*!< [23..23] USB clock enable                                                 */
      __IM  uint32_t            : 1;
      __IOM uint32_t CANCLKE    : 1;            /*!< [25..25] CAN clock enable                                                 */
      __IM  uint32_t            : 1;
      __IOM uint32_t BAKRCLKE    : 1;            /*!< [27..27] Bakr interface clock enable                                    */
      __IOM uint32_t PMUCLKE    : 1;            /*!< [28..28] Power interface clock enable                                     */
      __IOM uint32_t DACCLKE    : 1;            /*!< [29..29] DAC interface clock enable                                       */
    } APB1CLKEN_B;
  } ;
  
  union {
    __IOM uint32_t BD;                          /*!< (@ 0x00000020) Bakr domain control register (RCM_BD)                    */
    
    struct {
      __IOM uint32_t LXTEN      : 1;            /*!< [0..0] External Low Speed oscillator enable                               */
      __IM  uint32_t LXTRDYF    : 1;            /*!< [1..1] External Low Speed oscillator ready                                */
      __IOM uint32_t LXTBYP     : 1;            /*!< [2..2] External Low Speed oscillator bypass                               */
      __IM  uint32_t            : 5;
      __IOM uint32_t RTCSEL     : 2;            /*!< [9..8] RTC clock source selection                                         */
      __IM  uint32_t            : 5;
      __IOM uint32_t RTCEN      : 1;            /*!< [15..15] RTC clock enable                                                 */
      __IOM uint32_t BDRST      : 1;            /*!< [16..16] Bakr domain software reset                                     */
    } BD_B;
  } ;
  
  union {
    __IOM uint32_t CSTS;                        /*!< (@ 0x00000024) Control/status register (RCM_CSTS)                         */
    
    struct {
      __IOM uint32_t LIRCEN     : 1;            /*!< [0..0] Internal low speed oscillator enable                               */
      __IM  uint32_t LIRCRDYF   : 1;            /*!< [1..1] Internal low speed oscillator ready                                */
      __IM  uint32_t            : 22;
      __IOM uint32_t CLRRSTF    : 1;            /*!< [24..24] Remove reset flag                                                */
      __IM  uint32_t            : 1;
      __IOM uint32_t PINRSTF    : 1;            /*!< [26..26] PIN reset flag                                                   */
      __IOM uint32_t PWRRSTF    : 1;            /*!< [27..27] POR/PDR reset flag                                               */
      __IOM uint32_t SWRSTF     : 1;            /*!< [28..28] Software reset flag                                              */
      __IOM uint32_t IWDTRSTF   : 1;            /*!< [29..29] Independent watchdog reset flag                                  */
      __IOM uint32_t WWDTRSTF   : 1;            /*!< [30..30] Window watchdog reset flag                                       */
      __IOM uint32_t LPRRSTF    : 1;            /*!< [31..31] Low-power reset flag                                             */
    } CSTS_B;
  } ;
} RCM_T;                                     /*!< Size = 40 (0x28)                                                          */

/**
  * @brief DMA controller (DMA)
  */

typedef struct {                                /*!< (@ 0x40020000) DMA Structure                                              */
  
  union {
    __IM  uint32_t IF;                          /*!< (@ 0x00000000) DMA Interrupt status register (DMA_IF)                     */
    
    struct {
      __IM  uint32_t GIFC1      : 1;            /*!< [0..0] Channel 1 Global interrupt flag                                    */
      __IM  uint32_t EOTTFC1    : 1;            /*!< [1..1] Channel 1 Transfer Complete flag                                   */
      __IM  uint32_t MOTIFC1    : 1;            /*!< [2..2] Channel 1 Half Transfer Complete flag                              */
      __IM  uint32_t FOTIFC1    : 1;            /*!< [3..3] Channel 1 Transfer Error flag                                      */
      __IM  uint32_t GIFC2      : 1;            /*!< [4..4] Channel 2 Global interrupt flag                                    */
      __IM  uint32_t EOTTFC2    : 1;            /*!< [5..5] Channel 2 Transfer Complete flag                                   */
      __IM  uint32_t MOTIFC2    : 1;            /*!< [6..6] Channel 2 Half Transfer Complete flag                              */
      __IM  uint32_t FOTIFC2    : 1;            /*!< [7..7] Channel 2 Transfer Error flag                                      */
      __IM  uint32_t GIFC3      : 1;            /*!< [8..8] Channel 3 Global interrupt flag                                    */
      __IM  uint32_t EOTTFC3    : 1;            /*!< [9..9] Channel 3 Transfer Complete flag                                   */
      __IM  uint32_t MOTIFC3    : 1;            /*!< [10..10] Channel 3 Half Transfer Complete flag                            */
      __IM  uint32_t FOTIFC3    : 1;            /*!< [11..11] Channel 3 Transfer Error flag                                    */
      __IM  uint32_t GIFC4      : 1;            /*!< [12..12] Channel 4 Global interrupt flag                                  */
      __IM  uint32_t EOTTFC4    : 1;            /*!< [13..13] Channel 4 Transfer Complete flag                                 */
      __IM  uint32_t MOTIFC4    : 1;            /*!< [14..14] Channel 4 Half Transfer Complete flag                            */
      __IM  uint32_t FOTIFC4    : 1;            /*!< [15..15] Channel 4 Transfer Error flag                                    */
      __IM  uint32_t GIFC5      : 1;            /*!< [16..16] Channel 5 Global interrupt flag                                  */
      __IM  uint32_t EOTTFC5    : 1;            /*!< [17..17] Channel 5 Transfer Complete flag                                 */
      __IM  uint32_t MOTIFC5    : 1;            /*!< [18..18] Channel 5 Half Transfer Complete flag                            */
      __IM  uint32_t FOTIFC5    : 1;            /*!< [19..19] Channel 5 Transfer Error flag                                    */
      __IM  uint32_t GIFC6      : 1;            /*!< [20..20] Channel 6 Global interrupt flag                                  */
      __IM  uint32_t EOTTFC6    : 1;            /*!< [21..21] Channel 6 Transfer Complete flag                                 */
      __IM  uint32_t MOTIFC6    : 1;            /*!< [22..22] Channel 6 Half Transfer Complete flag                            */
      __IM  uint32_t FOTIFC6    : 1;            /*!< [23..23] Channel 6 Transfer Error flag                                    */
      __IM  uint32_t GIFC7      : 1;            /*!< [24..24] Channel 7 Global interrupt flag                                  */
      __IM  uint32_t TCIF7      : 1;            /*!< [25..25] Channel 7 Transfer Complete flag                                 */
      __IM  uint32_t MOTIFC7    : 1;            /*!< [26..26] Channel 7 Half Transfer Complete flag                            */
      __IM  uint32_t FOTIFC7    : 1;            /*!< [27..27] Channel 7 Transfer Error flag                                    */
    } IF_B;
  } ;
  
  union {
    __OM  uint32_t IFR;                         /*!< (@ 0x00000004) DMA Interrupt reset register (DMA_IFR)                     */
    
    struct {
      __OM  uint32_t RGIFC1     : 1;            /*!< [0..0] Channel 1 Global interrupt resetr                                  */
      __OM  uint32_t REOTIFC1   : 1;            /*!< [1..1] Channel 1 Transfer Complete reset                                  */
      __OM  uint32_t RMOTIFC1   : 1;            /*!< [2..2] Channel 1 Half Transfer reset                                      */
      __OM  uint32_t RFOTIFC1   : 1;            /*!< [3..3] Channel 1 Transfer Error reset                                     */
      __OM  uint32_t RGIFC2     : 1;            /*!< [4..4] Channel 2 Global interrupt reset                                   */
      __OM  uint32_t REOTIFC2   : 1;            /*!< [5..5] Channel 2 Transfer Complete reset                                  */
      __OM  uint32_t RMOTIFC2   : 1;            /*!< [6..6] Channel 2 Half Transfer reset                                      */
      __OM  uint32_t RFOTIFC2   : 1;            /*!< [7..7] Channel 2 Transfer Error reset                                     */
      __OM  uint32_t RGIFC3     : 1;            /*!< [8..8] Channel 3 Global interrupt reset                                   */
      __OM  uint32_t REOTIFC3   : 1;            /*!< [9..9] Channel 3 Transfer Complete reset                                  */
      __OM  uint32_t RMOTIFC3   : 1;            /*!< [10..10] Channel 3 Half Transfer reset                                    */
      __OM  uint32_t RFOTIFC3   : 1;            /*!< [11..11] Channel 3 Transfer Error reset                                   */
      __OM  uint32_t RGIFC4     : 1;            /*!< [12..12] Channel 4 Global interrupt reset                                 */
      __OM  uint32_t REOTIFC4   : 1;            /*!< [13..13] Channel 4 Transfer Complete reset                                */
      __OM  uint32_t RMOTIFC4   : 1;            /*!< [14..14] Channel 4 Half Transfer reset                                    */
      __OM  uint32_t RFOTIFC4   : 1;            /*!< [15..15] Channel 4 Transfer Error reset                                   */
      __OM  uint32_t RGIFC5     : 1;            /*!< [16..16] Channel 5 Global interrupt reset                                 */
      __OM  uint32_t REOTIFC5   : 1;            /*!< [17..17] Channel 5 Transfer Complete reset                                */
      __OM  uint32_t RMOTIFC5   : 1;            /*!< [18..18] Channel 5 Half Transfer reset                                    */
      __OM  uint32_t RFOTIFC5   : 1;            /*!< [19..19] Channel 5 Transfer Error reset                                   */
      __OM  uint32_t RGIFC6     : 1;            /*!< [20..20] Channel 6 Global interrupt reset                                 */
      __OM  uint32_t REOTIFC6   : 1;            /*!< [21..21] Channel 6 Transfer Complete reset                                */
      __OM  uint32_t RMOTIFC6   : 1;            /*!< [22..22] Channel 6 Half Transfer reset                                    */
      __OM  uint32_t RFOTIFC6   : 1;            /*!< [23..23] Channel 6 Transfer Error reset                                   */
      __OM  uint32_t RGIFC7     : 1;            /*!< [24..24] Channel 7 Global interrupt reset                                 */
      __OM  uint32_t REOTIFC7   : 1;            /*!< [25..25] Channel 7 Transfer Complete reset                                */
      __OM  uint32_t RMOTIFC7   : 1;            /*!< [26..26] Channel 7 Half Transfer reset                                    */
      __OM  uint32_t RFOTIFC7   : 1;            /*!< [27..27] Channel 7 Transfer Error reset                                   */
    } IFR_B;
  } ;
  
  union {
    __IOM uint32_t SRC1;                        /*!< (@ 0x00000008) DMA channel 1 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC1_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC1;                      /*!< (@ 0x0000000C) DMA channel 1 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC1_B;
  } ;
  
  union {
    __IOM uint32_t PAC1;                        /*!< (@ 0x00000010) DMA channel 1 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC1_B;
  } ;
  
  union {
    __IOM uint32_t MAC1;                        /*!< (@ 0x00000014) DMA channel 1 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC1_B;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t SRC2;                        /*!< (@ 0x0000001C) DMA channel 2 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC2_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC2;                      /*!< (@ 0x00000020) DMA channel 2 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC2_B;
  } ;
  
  union {
    __IOM uint32_t PAC2;                        /*!< (@ 0x00000024) DMA channel 2 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC2_B;
  } ;
  
  union {
    __IOM uint32_t MAC2;                        /*!< (@ 0x00000028) DMA channel 2 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC2_B;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t SRC3;                        /*!< (@ 0x00000030) DMA channel 3 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC3_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC3;                      /*!< (@ 0x00000034) DMA channel 3 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC3_B;
  } ;
  
  union {
    __IOM uint32_t PAC3;                        /*!< (@ 0x00000038) DMA channel 3 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC3_B;
  } ;
  
  union {
    __IOM uint32_t MAC3;                        /*!< (@ 0x0000003C) DMA channel 3 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC3_B;
  } ;
  __IM  uint32_t  RESERVED2;
  
  union {
    __IOM uint32_t SRC4;                        /*!< (@ 0x00000044) DMA channel 4 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC4_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC4;                      /*!< (@ 0x00000048) DMA channel 4 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC4_B;
  } ;
  
  union {
    __IOM uint32_t PAC4;                        /*!< (@ 0x0000004C) DMA channel 4 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC4_B;
  } ;
  
  union {
    __IOM uint32_t MAC4;                        /*!< (@ 0x00000050) DMA channel 4 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC4_B;
  } ;
  __IM  uint32_t  RESERVED3;
  
  union {
    __IOM uint32_t SRC5;                        /*!< (@ 0x00000058) DMA channel 5 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC5_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC5;                      /*!< (@ 0x0000005C) DMA channel 5 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC5_B;
  } ;
  
  union {
    __IOM uint32_t PAC5;                        /*!< (@ 0x00000060) DMA channel 5 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC5_B;
  } ;
  
  union {
    __IOM uint32_t MAC5;                        /*!< (@ 0x00000064) DMA channel 5 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC5_B;
  } ;
  __IM  uint32_t  RESERVED4;
  
  union {
    __IOM uint32_t SRC6;                        /*!< (@ 0x0000006C) DMA channel 6 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC6_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC6;                      /*!< (@ 0x00000070) DMA channel 6 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC6_B;
  } ;
  
  union {
    __IOM uint32_t PAC6;                        /*!< (@ 0x00000074) DMA channel 6 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC6_B;
  } ;
  
  union {
    __IOM uint32_t MAC6;                        /*!< (@ 0x00000078) DMA channel 6 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC6_B;
  } ;
  __IM  uint32_t  RESERVED5;
  
  union {
    __IOM uint32_t SRC7;                        /*!< (@ 0x00000080) DMA channel 7 configuration register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t EOTIEN     : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t MOTIEN     : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t FOTIEN     : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DOT        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t LOOP       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PLOOP      : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MLOOP      : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PWID       : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MWID       : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t M2MEN      : 1;            /*!< [14..14] Memory to memory mode                                            */
    } SRC7_B;
  } ;
  
  union {
    __IOM uint32_t CNTTC7;                      /*!< (@ 0x00000084) DMA channel 7 number of data register                      */
    
    struct {
      __IOM uint32_t CNTTC      : 16;           /*!< [15..0] Number of data to transfer                                        */
    } CNTTC7_B;
  } ;
  
  union {
    __IOM uint32_t PAC7;                        /*!< (@ 0x00000088) DMA channel 7 peripheral address register                  */
    
    struct {
      __IOM uint32_t PAC        : 32;           /*!< [31..0] Peripheral address                                                */
    } PAC7_B;
  } ;
  
  union {
    __IOM uint32_t MAC7;                        /*!< (@ 0x0000008C) DMA channel 7 memory address register                      */
    
    struct {
      __IOM uint32_t MAC        : 32;           /*!< [31..0] Memory address                                                    */
    } MAC7_B;
  } ;
} DMA1_T;                                     /*!< Size = 144 (0x90)                                                         */

typedef struct
{
 /**
  * @brief    DMA Channel setup register
   */
 union
 {
   __IOM uint32_t SRC;

   struct
   {
     __IOM  uint32_t EN          : 1;
     __IOM  uint32_t EOTIEN      : 1;
     __IOM  uint32_t MOTIEN      : 1;
     __IOM  uint32_t FOTIEN      : 1;
     __IOM  uint32_t DOT         : 1;
     __IOM  uint32_t LOOP        : 1;
     __IOM  uint32_t PLOOP       : 1;
     __IOM  uint32_t MLOOP       : 1;
     __IOM  uint32_t PWID        : 2;
     __IOM  uint32_t MWID        : 2;
     __IOM  uint32_t PL          : 2;
     __IOM  uint32_t M2MEN       : 1;
     __IM  uint32_t RESERVED    : 17;
   } SRC_B;
 } ;

 /**
  * @brief    DMA Channel transfer number register
   */
 union
 {
   __IOM uint32_t CNTTC;

   struct
   {
     __IOM uint32_t CNTTC     :16;
     __IM  uint32_t RESERVED    : 16;
   } CNTTC_B;
 };

 /**
  * @brief    DMA Channel peripheral address register
   */
 union
 {
   __IOM uint32_t PAC;

   struct
   {
     __IOM uint32_t PAC     :32;
   } PAC_B;
 };

 /**
  * @brief    DMA Channel memory address register
   */
 union
 {
   __IOM uint32_t MAC;

   struct
   {
     __IOM uint32_t MAC     :32;
   } MAC_B;
 };

} DMA_Channel_T;

/**
  * @brief Universal synchronous asynchronous receiver transmitter (USART1)
  */

typedef struct {                                /*!< (@ 0x40013800) USART1 Structure                                           */
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x00000000) Status register                                            */
    
    struct {
      __IM  uint32_t PEF        : 1;            /*!< [0..0] Parity error                                                       */
      __IM  uint32_t FEF        : 1;            /*!< [1..1] Framing error                                                      */
      __IM  uint32_t NEF        : 1;            /*!< [2..2] Noise error flag                                                   */
      __IM  uint32_t OVREF      : 1;            /*!< [3..3] Overrun error                                                      */
      __IM  uint32_t IDLEF      : 1;            /*!< [4..4] IDLE line detected                                                 */
      __IOM uint32_t RXBNEF     : 1;            /*!< [5..5] Read data register not empty                                       */
      __IOM uint32_t TXCF       : 1;            /*!< [6..6] Transmission complete                                              */
      __IM  uint32_t TXBEF      : 1;            /*!< [7..7] Transmit data register empty                                       */
      __IOM uint32_t LBDF       : 1;            /*!< [8..8] LIN break detection flag                                           */
      __IOM uint32_t CTSF       : 1;            /*!< [9..9] CTS flag                                                           */
    } STS_B;
  } ;
  
  union {
    __IOM uint32_t DATA;                        /*!< (@ 0x00000004) TX Buffer Data Register                                    */
    
    struct {
      __IOM uint32_t DATA       : 9;            /*!< [8..0] Data value                                                         */
    } DATA_B;
  } ;
  
  union {
    __IOM uint32_t BR;                          /*!< (@ 0x00000008) Baud rate register                                         */
    
    struct {
      __IOM uint32_t FRACTION   : 4;            /*!< [3..0] fraction of USARTDIV                                               */
      __IOM uint32_t MANTISSA   : 12;           /*!< [15..4] mantissa of USARTDIV                                              */
    } BR_B;
  } ;
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x0000000C) Control register 1                                         */
    
    struct {
      __IOM uint32_t TXBK       : 1;            /*!< [0..0] Send break                                                         */
      __IOM uint32_t RXWUP      : 1;            /*!< [1..1] Receiver wakeup                                                    */
      __IOM uint32_t RXEN       : 1;            /*!< [2..2] Receiver enable                                                    */
      __IOM uint32_t TXEN       : 1;            /*!< [3..3] Transmitter enable                                                 */
      __IOM uint32_t IDLEIE     : 1;            /*!< [4..4] IDLE interrupt enable                                              */
      __IOM uint32_t RXBNEIE    : 1;            /*!< [5..5] RXNE interrupt enable                                              */
      __IOM uint32_t TXCIE      : 1;            /*!< [6..6] Transmission complete interrupt enable                             */
      __IOM uint32_t TXBEIE     : 1;            /*!< [7..7] TXE interrupt enable                                               */
      __IOM uint32_t PEIE       : 1;            /*!< [8..8] PE interrupt enable                                                */
      __IOM uint32_t PMSEL      : 1;            /*!< [9..9] Parity selection                                                   */
      __IOM uint32_t PCEN       : 1;            /*!< [10..10] Parity control enable                                            */
      __IOM uint32_t WUPM       : 1;            /*!< [11..11] Wakeup method                                                    */
      __IOM uint32_t WLS        : 1;            /*!< [12..12] Word length                                                      */
      __IOM uint32_t UEN        : 1;            /*!< [13..13] USART enable                                                     */
    } CTRL1_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000010) Control register 2                                         */
    
    struct {
      __IOM uint32_t ADDR       : 4;            /*!< [3..0] Address of the USART node                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t LBDL       : 1;            /*!< [5..5] lin break detection length                                         */
      __IOM uint32_t LBDIE      : 1;            /*!< [6..6] LIN break detection interrupt enable                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t LBCEN      : 1;            /*!< [8..8] Last bit clock pulse                                               */
      __IOM uint32_t CLKPHA     : 1;            /*!< [9..9] Clock phase                                                        */
      __IOM uint32_t CLKPOL     : 1;            /*!< [10..10] Clock polarity                                                   */
      __IOM uint32_t CKPEN      : 1;            /*!< [11..11] Clock enable                                                     */
      __IOM uint32_t STOPB      : 2;            /*!< [13..12] STOP bits                                                        */
      __IOM uint32_t LINEN      : 1;            /*!< [14..14] LIN mode enable                                                  */
    } CTRL2_B;
  } ;
  
  union {
    __IOM uint32_t CTRL3;                       /*!< (@ 0x00000014) Control register 3                                         */
    
    struct {
      __IOM uint32_t ERRIE      : 1;            /*!< [0..0] Error interrupt enable                                             */
      __IOM uint32_t IRDAEN     : 1;            /*!< [1..1] IrDA mode enable                                                   */
      __IOM uint32_t IRDALP     : 1;            /*!< [2..2] IrDA low-power                                                     */
      __IOM uint32_t HDEN       : 1;            /*!< [3..3] Half-duplex selection                                              */
      __IOM uint32_t NACKEN     : 1;            /*!< [4..4] Smartcard NACK enable                                              */
      __IOM uint32_t SCEN       : 1;            /*!< [5..5] Smartcard mode enable                                              */
      __IOM uint32_t RXDMAEN    : 1;            /*!< [6..6] DMA enable receiver                                                */
      __IOM uint32_t TXDMAEN    : 1;            /*!< [7..7] DMA enable transmitter                                             */
      __IOM uint32_t RTSEN      : 1;            /*!< [8..8] RTS enable                                                         */
      __IOM uint32_t CTSEN      : 1;            /*!< [9..9] CTS enable                                                         */
      __IOM uint32_t CTSIE      : 1;            /*!< [10..10] CTS interrupt enable                                             */
    } CTRL3_B;
  } ;
  
  union {
    __IOM uint32_t GTDIV;                       /*!< (@ 0x00000018) Guard time and divider number register                     */
    
    struct {
      __IOM uint32_t DIV        : 8;            /*!< [7..0] Prescaler value                                                    */
      __IOM uint32_t GT         : 8;            /*!< [15..8] Guard time value                                                  */
    } GTDIV_B;
  } ;
} USART_T;                                  /*!< Size = 28 (0x1c)                                                          */


typedef struct {
    /** Control register 1 */
    union {
        __IOM uint32_t CTRL1;
        
        struct {
            __IOM  uint32_t CLKPHA       : 1;
            __IOM  uint32_t CLKPOL       : 1;
            __IOM  uint32_t MSTMODE      : 1;
            __IOM  uint32_t BRC             : 3;
            __IOM  uint32_t SPIEN         : 1;
            __IOM  uint32_t LSBF         : 1;
            __IOM  uint32_t ISS          : 1;
            __IOM  uint32_t SSC          : 1;
            __IOM  uint32_t UMRXO        : 1;
            __IOM  uint32_t DFL          : 1;
            __IOM  uint32_t CRCNXT       : 1;
            __IOM  uint32_t CRCEN        : 1;
            __IOM  uint32_t BMTX         : 1;
            __IOM  uint32_t BMEN         : 1;
            __IM   uint32_t RESERVED    : 16;
        } CTRL1_B;
    };
    
    /** Control register 2 */
    union {
        __IOM uint32_t CTRL2;
        
        struct {
            __IOM  uint32_t RX_DMAEN       : 1;
            __IOM  uint32_t TX_DMAEN       : 1;
            __IOM  uint32_t SSOEN       : 1;
            __IM   uint32_t RESERVED1    : 2;
            __IOM  uint32_t ERRIE       : 1;
            __IOM  uint32_t RXBNEIE       : 1;
            __IOM  uint32_t TXBEIE       : 1;
            __IM   uint32_t RESERVED2    : 24;
        } CTRL2_B;
    };
    
    /** Status register */
    union {
        __IOM uint32_t STS;
        
        struct {
            __IM  uint32_t RXBNEF       : 1;
            __IM  uint32_t TXBEF           : 1;
            __IM  uint32_t ST           : 1;
            __IM  uint32_t UDF           : 1;
            __IOM uint32_t CRCEF           : 1;
            __IM  uint32_t MEF           : 1;
            __IM  uint32_t RXOF           : 1;
            __IM  uint32_t BUSYF           : 1;
            __IM  uint32_t RESERVED        : 24;
        } STS_B;
    };
    
    /** Data register */
    union {
        __IOM uint32_t DATA;
        
        struct {
            __IOM  uint32_t DATA           : 16;
            __IM  uint32_t RESERVED        : 16;
        } DATA_B;
    };
    
    /** CRC polynomial register */
    union {
        __IOM uint32_t CRCPOLY;
        
        struct {
            __IOM  uint32_t CRCPOLY       : 16;
            __IM  uint32_t RESERVED        : 16;
        } CRCPOLY_B;
    };
    
    /** Receive CRC register */
    union {
        __IOM uint32_t RXCRC;
        
        struct {
            __IOM  uint32_t RXCRC       : 16;
            __IM  uint32_t RESERVED        : 16;
        }RXCRC_B;
    };
    
    /** Transmit CRC register */
    union {
        __IOM uint32_t TXCRC;
        
        struct {
            __IOM  uint32_t TXCRC       : 16;
            __IM  uint32_t RESERVED        : 16;
        }TXCRC_B;
    };
} SPI_T;                                    /*!< Size = 36 (0x24)                                                          */

/**
  * @brief Advanced timer (TMR)
  */

typedef struct {                                /*!< (@ 0x40012C00) TMR Structure                                             */
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000000) control register 1                                         */
    
    struct {
      __IOM uint32_t CNTEN      : 1;            /*!< [0..0] Counter enable                                                     */
      __IOM uint32_t NGUE       : 1;            /*!< [1..1] Update disable                                                     */
      __IOM uint32_t UES        : 1;            /*!< [2..2] Update request source                                              */
      __IOM uint32_t SPMEN      : 1;            /*!< [3..3] One-pulse mode                                                     */
      __IOM uint32_t CNTDIR     : 1;            /*!< [4..4] Direction                                                          */
      __IOM uint32_t CNTMODE    : 2;            /*!< [6..5] Center-aligned mode selection                                      */
      __IOM uint32_t ARBEN      : 1;            /*!< [7..7] Auto-reload preload enable                                         */
      __IOM uint32_t CKDR       : 2;            /*!< [9..8] Clock division                                                     */
    } CTRL1_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000004) control register 2                                         */
    
    struct {
      __IOM uint32_t CCBEN      : 1;            /*!< [0..0] Capture/compare preloaded control                                  */
      __IM  uint32_t            : 1;
      __IOM uint32_t CCUS       : 1;            /*!< [2..2] Capture/compare control update selection                           */
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] Capture/compare DMA selection                                      */
      __IOM uint32_t MMFC       : 3;            /*!< [6..4] Master mode selection                                              */
      __IOM uint32_t TI1IS      : 1;            /*!< [7..7] TI1 selection                                                      */
      __IOM uint32_t CH1ISO     : 1;            /*!< [8..8] Output Idle state 1                                                */
      __IOM uint32_t CH1NISO    : 1;            /*!< [9..9] Output Idle state 1                                                */
      __IOM uint32_t CH2ISO     : 1;            /*!< [10..10] Output Idle state 2                                              */
      __IOM uint32_t CH2NISO    : 1;            /*!< [11..11] Output Idle state 2                                              */
      __IOM uint32_t CH3ISO     : 1;            /*!< [12..12] Output Idle state 3                                              */
      __IOM uint32_t CH3NISO    : 1;            /*!< [13..13] Output Idle state 3                                              */
      __IOM uint32_t CH4ISO     : 1;            /*!< [14..14] Output Idle state 4                                              */
    } CTRL2_B;
  } ;
  
  union {
    __IOM uint32_t SMCTRL;                      /*!< (@ 0x00000008) slave mode control register                                */
    
    struct {
      __IOM uint32_t SMFC       : 3;            /*!< [2..0] Slave mode selection                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t ITC        : 3;            /*!< [6..4] Trigger selection                                                  */
      __IOM uint32_t MSMEN      : 1;            /*!< [7..7] Master/Slave mode                                                  */
      __IOM uint32_t ETFC       : 4;            /*!< [11..8] External trigger filter                                           */
      __IOM uint32_t ETDC       : 2;            /*!< [13..12] External trigger prescaler                                       */
      __IOM uint32_t ECM2EN     : 1;            /*!< [14..14] External clock enable                                            */
      __IOM uint32_t ETPC       : 1;            /*!< [15..15] External trigger polarity                                        */
    } SMCTRL_B;
  } ;
  
  union {
    __IOM uint32_t DIEN;                        /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
    
    struct {
      __IOM uint32_t UDIEN      : 1;            /*!< [0..0] Update interrupt enable                                            */
      __IOM uint32_t CH1CCIEN   : 1;            /*!< [1..1] Capture/Compare 1 interrupt enable                                 */
      __IOM uint32_t CH2CCIEN   : 1;            /*!< [2..2] Capture/Compare 2 interrupt enable                                 */
      __IOM uint32_t CH3CCIEN   : 1;            /*!< [3..3] Capture/Compare 3 interrupt enable                                 */
      __IOM uint32_t CH4CCIEN   : 1;            /*!< [4..4] Capture/Compare 4 interrupt enable                                 */
      __IOM uint32_t CCUIEN     : 1;            /*!< [5..5] COM interrupt enable                                               */
      __IOM uint32_t TRGIEN     : 1;            /*!< [6..6] Trigger interrupt enable                                           */
      __IOM uint32_t BRKIEN     : 1;            /*!< [7..7] Break interrupt enable                                             */
      __IOM uint32_t UDEN       : 1;            /*!< [8..8] Update DMA request enable                                          */
      __IOM uint32_t CH1CCDEN   : 1;            /*!< [9..9] Capture/Compare 1 DMA request enable                               */
      __IOM uint32_t CH2CCDEN   : 1;            /*!< [10..10] Capture/Compare 2 DMA request enable                             */
      __IOM uint32_t CH3CCDEN   : 1;            /*!< [11..11] Capture/Compare 3 DMA request enable                             */
      __IOM uint32_t CH4CCDEN   : 1;            /*!< [12..12] Capture/Compare 4 DMA request enable                             */
      __IOM uint32_t CMDEN      : 1;            /*!< [13..13] COM DMA request enable                                           */
      __IOM uint32_t TDEN       : 1;            /*!< [14..14] Trigger DMA request enable                                       */
    } DIEN_B;
  } ;
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x00000010) status register                                            */
    
    struct {
      __IOM uint32_t UDIF       : 1;            /*!< [0..0] Update interrupt flag                                              */
      __IOM uint32_t CH1CCIF    : 1;            /*!< [1..1] Capture/compare 1 interrupt flag                                   */
      __IOM uint32_t CH2CCIF    : 1;            /*!< [2..2] Capture/Compare 2 interrupt flag                                   */
      __IOM uint32_t CH3CCIF    : 1;            /*!< [3..3] Capture/Compare 3 interrupt flag                                   */
      __IOM uint32_t CH4CCIF    : 1;            /*!< [4..4] Capture/Compare 4 interrupt flag                                   */
      __IOM uint32_t CCUIF      : 1;            /*!< [5..5] COM interrupt flag                                                 */
      __IOM uint32_t TRGIF      : 1;            /*!< [6..6] Trigger interrupt flag                                             */
      __IOM uint32_t BRKIF      : 1;            /*!< [7..7] Break interrupt flag                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t CH1RCF     : 1;            /*!< [9..9] Capture/Compare 1 overcapture flag                                 */
      __IOM uint32_t CH2RCF     : 1;            /*!< [10..10] Capture/compare 2 overcapture flag                               */
      __IOM uint32_t CH3RCF     : 1;            /*!< [11..11] Capture/Compare 3 overcapture flag                               */
      __IOM uint32_t CH4RCF     : 1;            /*!< [12..12] Capture/Compare 4 overcapture flag                               */
    } STS_B;
  } ;
  
  union {
    __OM  uint32_t SCEG;                        /*!< (@ 0x00000014) event generation register                                  */
    
    struct {
      __OM  uint32_t UEG        : 1;            /*!< [0..0] Update generation                                                  */
      __OM  uint32_t CH1CCG     : 1;            /*!< [1..1] Capture/compare 1 generation                                       */
      __OM  uint32_t CH2CCG     : 1;            /*!< [2..2] Capture/compare 2 generation                                       */
      __OM  uint32_t CH3CCG     : 1;            /*!< [3..3] Capture/compare 3 generation                                       */
      __OM  uint32_t CH4CCG     : 1;            /*!< [4..4] Capture/compare 4 generation                                       */
      __OM  uint32_t CCUEG      : 1;            /*!< [5..5] Capture/Compare control update generation                          */
      __OM  uint32_t TEG        : 1;            /*!< [6..6] Trigger generation                                                 */
      __OM  uint32_t BEG        : 1;            /*!< [7..7] Break generation                                                   */
    } SCEG_B;
  } ;
  
  union {
    union {
      __IOM uint32_t CCM1;               /*!< (@ 0x00000018) capture/compare mode register 1 (Compare mode)                */
      
      struct {
        __IOM uint32_t CC1MS    : 2;            /*!< [1..0] Capture/Compare 1 selection                                        */
        __IOM uint32_t OC1FEN   : 1;            /*!< [2..2] Output Compare 1 fast enable                                       */
        __IOM uint32_t OC1BEN   : 1;            /*!< [3..3] Output Compare 1 preload enable                                    */
        __IOM uint32_t OC1MS    : 3;            /*!< [6..4] Output Compare 1 mode                                              */
        __IOM uint32_t OC1CEN   : 1;            /*!< [7..7] Output Compare 1 clear enable                                      */
        __IOM uint32_t CC2MS    : 2;            /*!< [9..8] Capture/Compare 2 selection                                        */
        __IOM uint32_t OC2FEN   : 1;            /*!< [10..10] Output Compare 2 fast enable                                     */
        __IOM uint32_t OC2BEN   : 1;            /*!< [11..11] Output Compare 2 preload enable                                  */
        __IOM uint32_t OC2MS    : 3;            /*!< [14..12] Output Compare 2 mode                                            */
        __IOM uint32_t OC2CEN   : 1;            /*!< [15..15] Output Compare 2 clear enable                                    */
      } CCM1_COMPARE_B;
    
                                                /*!< (@ 0x00000018) capture/compare mode register 1 (Capture mode)               */
      struct {
        __IOM uint32_t CC1MS    : 2;            /*!< [1..0] Capture/Compare 1 selection                                        */
        __IOM uint32_t IC1D     : 2;            /*!< [3..2] Input capture 1 prescaler                                          */
        __IOM uint32_t IC1FC    : 4;            /*!< [7..4] Input capture 1 filter                                             */
        __IOM uint32_t CC2MS    : 2;            /*!< [9..8] Capture/Compare 2 selection                                        */
        __IOM uint32_t IC2D     : 2;            /*!< [11..10] Input capture 2 prescaler                                        */
        __IOM uint32_t IC2FC    : 4;            /*!< [15..12] Input capture 2 filter                                           */
      } CCM1_CAPTURE_B;
    } ;
  };
  
  union {
 
      __IOM uint32_t CCM2;                      /*!< (@ 0x0000001C) capture/compare mode register 2 (Compare mode)                */
      
      struct {
        __IOM uint32_t CC3MS    : 2;            /*!< [1..0] Capture/Compare 3 selection                                        */
        __IOM uint32_t OC3FEN   : 1;            /*!< [2..2] Output compare 3 fast enable                                       */
        __IOM uint32_t OC3BEN   : 1;            /*!< [3..3] Output compare 3 preload enable                                    */
        __IOM uint32_t OC3MS    : 3;            /*!< [6..4] Output compare 3 mode                                              */
        __IOM uint32_t OC3CEN   : 1;            /*!< [7..7] Output compare 3 clear enable                                      */
        __IOM uint32_t CC4MS    : 2;            /*!< [9..8] Capture/Compare 4 selection                                        */
        __IOM uint32_t OC4FEN   : 1;            /*!< [10..10] Output compare 4 fast enable                                     */
        __IOM uint32_t OC4BEN   : 1;            /*!< [11..11] Output compare 4 preload enable                                  */
        __IOM uint32_t OC4MS    : 3;            /*!< [14..12] Output compare 4 mode                                            */
        __IOM uint32_t OC4CEN   : 1;            /*!< [15..15] Output compare 4 clear enable                                    */
      } CCM2_COMPARE_B;
 
                                                /*!< (@ 0x0000001C) capture/compare mode register 2 (Capture mode)               */ 
      struct {
        __IOM uint32_t CC3MS    : 2;            /*!< [1..0] Capture/compare 3 selection                                        */
        __IOM uint32_t IC3D     : 2;            /*!< [3..2] Input capture 3 prescaler                                          */
        __IOM uint32_t IC3FC    : 4;            /*!< [7..4] Input capture 3 filter                                             */
        __IOM uint32_t CC4MS    : 2;            /*!< [9..8] Capture/Compare 4 selection                                        */
        __IOM uint32_t IC4D     : 2;            /*!< [11..10] Input capture 4 prescaler                                        */
        __IOM uint32_t IC4FC    : 4;            /*!< [15..12] Input capture 4 filter                                           */
      } CCM2_CAPTURE_B;
  };
  
  union {
    __IOM uint32_t CHCTRL;                      /*!< (@ 0x00000020) capture/compare enable register                            */
    
    struct {
      __IOM uint32_t CH1CCEN    : 1;            /*!< [0..0] Capture/Compare 1 output enable                                    */
      __IOM uint32_t CH1CCP     : 1;            /*!< [1..1] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CH1OCNEN   : 1;            /*!< [2..2] Capture/Compare 1 complementary output enable                      */
      __IOM uint32_t CH1OCNP    : 1;            /*!< [3..3] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CH2CCEN    : 1;            /*!< [4..4] Capture/Compare 2 output enable                                    */
      __IOM uint32_t CH2CCP     : 1;            /*!< [5..5] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CH2OCNEN   : 1;            /*!< [6..6] Capture/Compare 2 complementary output enable                      */
      __IOM uint32_t CH2OCNP    : 1;            /*!< [7..7] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CH3CCEN    : 1;            /*!< [8..8] Capture/Compare 3 output enable                                    */
      __IOM uint32_t CH3CCP     : 1;            /*!< [9..9] Capture/Compare 3 output Polarity                                  */
      __IOM uint32_t CH3OCNEN   : 1;            /*!< [10..10] Capture/Compare 3 complementary output enable                    */
      __IOM uint32_t CH3OCNP    : 1;            /*!< [11..11] Capture/Compare 3 output Polarity                                */
      __IOM uint32_t CH4CCEN    : 1;            /*!< [12..12] Capture/Compare 4 output enable                                  */
      __IOM uint32_t CH4CCP     : 1;            /*!< [13..13] Capture/Compare 3 output Polarity                                */
    } CHCTRL_B;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] counter value                                                     */
    } CNT_B;
  } ;
  
  union {
    __IOM uint32_t DIV;                         /*!< (@ 0x00000028) prescaler                                                  */
    
    struct {
      __IOM uint32_t DIV        : 16;           /*!< [15..0] Prescaler value                                                   */
    } DIV_B;
  } ;
  
  union {
    __IOM uint32_t AOUTORLD;                    /*!< (@ 0x0000002C) auto-reload register                                       */
    
    struct {
      __IOM uint32_t AOUTORLD   : 16;           /*!< [15..0] Auto-reload value                                                 */
    } AOUTORLD_B;
  } ;
  
  union {
    __IOM uint32_t REPCNT;                      /*!< (@ 0x00000030) Repeat count register                                      */
    
    struct {
      __IOM uint32_t REPCNT     : 16;           /*!< [15..0] Auto-reload value                                                 */
    } REPCNT_B;
  } ;
  
  union {
    __IOM uint32_t CH1CC;                       /*!< (@ 0x00000034) capture/compare register 1                                 */
    
    struct {
      __IOM uint32_t CH1CC      : 16;           /*!< [15..0] Capture/Compare 1 value                                           */
    } CH1CC_B;
  } ;
  
  union {
    __IOM uint32_t CH2CC;                       /*!< (@ 0x00000038) capture/compare register 2                                 */
    
    struct {
      __IOM uint32_t CH2CC      : 16;           /*!< [15..0] Capture/Compare 2 value                                           */
    } CH2CC_B;
  } ;
  
  union {
    __IOM uint32_t CH3CC;                       /*!< (@ 0x0000003C) capture/compare register 3                                 */
    
    struct {
      __IOM uint32_t CH3CC      : 16;           /*!< [15..0] Capture/Compare 3 value                                           */
    } CH3CC_B;
  } ;
  
  union {
    __IOM uint32_t CH4CC;                       /*!< (@ 0x00000040) capture/compare register 4                                 */
    
    struct {
      __IOM uint32_t CH4CC      : 16;           /*!< [15..0] Capture/Compare 4 value                                           */
    } CH4CC_B;
  } ;
  
  union {
    __IOM uint32_t BDT;                         /*!< (@ 0x00000044) Brake and dead zone registers                              */
    
    struct {
      __IOM uint32_t DTS        : 8;            /*!< [7..0] Dead-time generator setup                                          */
      __IOM uint32_t PROTCFG    : 2;            /*!< [9..8] Lock configuration                                                 */
      __IOM uint32_t IMOS       : 1;            /*!< [10..10] Off-state selection for Idle mode                                */
      __IOM uint32_t RMOS       : 1;            /*!< [11..11] Off-state selection for Run mode                                 */
      __IOM uint32_t BRKEN      : 1;            /*!< [12..12] Break enable                                                     */
      __IOM uint32_t BRKPOL     : 1;            /*!< [13..13] Break polarity                                                   */
      __IOM uint32_t AOEN       : 1;            /*!< [14..14] Automatic output enable                                          */
      __IOM uint32_t WOEN       : 1;            /*!< [15..15] Main output enable                                               */
    } BDT_B;
  } ;
  
  union {
    __IOM uint32_t DCTRL;                       /*!< (@ 0x00000048) DMA control register                                       */
    
    struct {
      __IOM uint32_t DBA        : 5;            /*!< [4..0] DMA base address                                                   */
      __IM  uint32_t            : 3;
      __IOM uint32_t DBL        : 5;            /*!< [12..8] DMA burst length                                                  */
    } DCTRL_B;
  } ;
  
  union {
    __IOM uint32_t DMAB;                        /*!< (@ 0x0000004C) Consecutive DMA addresses                                  */
    
    struct {
      __IOM uint32_t DMAB       : 16;           /*!< [15..0] DMA register for burst accesses                                   */
    } DMAB_B;
  } ;
} TMR_T;                                    /*!< Size = 80 (0x50)                                                          */


/**
  * @brief Analog to digital converter (ADC)
  */

typedef struct {                                /*!< (@ 0x40012400) ADC1 Structure                                             */
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x00000000) status register                                            */
    
    struct {
      __IOM uint32_t AWDF       : 1;            /*!< [0..0] Analog watchdog flag                                               */
      __IOM uint32_t CCF        : 1;            /*!< [1..1] Regular channel end of conversion                                  */
      __IOM uint32_t IJEOCF     : 1;            /*!< [2..2] Injected channel end of conversion                                 */
      __IOM uint32_t IJSTRF     : 1;            /*!< [3..3] Injected channel start flag                                        */
      __IOM uint32_t STRT       : 1;            /*!< [4..4] Regular channel start flag                                         */
    } STS_B;
  } ;
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000004) control register 1                                         */
    
    struct {
      __IOM uint32_t AWDCS      : 5;            /*!< [4..0] Analog watchdog channel select bits                                */
      __IOM uint32_t EOCIEN     : 1;            /*!< [5..5] Interrupt enable for EOC                                           */
      __IOM uint32_t AWDIEN     : 1;            /*!< [6..6] Analog watchdog interrupt enable                                   */
      __IOM uint32_t IJEOCIEN   : 1;            /*!< [7..7] Interrupt enable for injected channels                             */
      __IOM uint32_t SMEN       : 1;            /*!< [8..8] Scan mode                                                          */
      __IOM uint32_t AWDSC      : 1;            /*!< [9..9] Enable the watchdog on a single channel in scan mode               */
      __IOM uint32_t IJAEN      : 1;            /*!< [10..10] Automatic injected group conversion                              */
      __IOM uint32_t RGDMEN     : 1;            /*!< [11..11] Discontinuous mode on regular channels                           */
      __IOM uint32_t IJDMEN     : 1;            /*!< [12..12] Discontinuous mode on injected channels                          */
      __IOM uint32_t DMCC       : 3;            /*!< [15..13] Discontinuous mode channel count                                 */
      __IOM uint32_t DMS        : 4;            /*!< [19..16] Dual mode selection                                              */
      __IM  uint32_t            : 2;
      __IOM uint32_t IJAWDEN    : 1;            /*!< [22..22] Analog watchdog enable on injected channels                      */
      __IOM uint32_t RGAWDEN    : 1;            /*!< [23..23] Analog watchdog enable on regular channels                       */
    } CTRL1_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000008) control register 2                                         */
    
    struct {
      __IOM uint32_t ADCON      : 1;            /*!< [0..0] A/D converter ON / OFF                                             */
      __IOM uint32_t CCM        : 1;            /*!< [1..1] Continuous conversion                                              */
      __IOM uint32_t CALSTR     : 1;            /*!< [2..2] A/D calibration                                                    */
      __IOM uint32_t CALRST     : 1;            /*!< [3..3] Reset calibration                                                  */
      __IM  uint32_t            : 4;
      __IOM uint32_t DMAEN      : 1;            /*!< [8..8] Direct memory access mode                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t DAM        : 1;            /*!< [11..11] Data alignment                                                   */
      __IOM uint32_t IJEXTSEL   : 3;            /*!< [14..12] External event select for injected group                         */
      __IOM uint32_t IJEXTGEN   : 1;            /*!< [15..15] External trigger conversion mode for injected channels           */
      __IM  uint32_t            : 1;
      __IOM uint32_t RGEXTSEL   : 3;            /*!< [19..17] External event select for regular group                          */
      __IOM uint32_t RGEXTGEN   : 1;            /*!< [20..20] External trigger conversion mode for regular channels            */
      __IOM uint32_t IJSWSTR    : 1;            /*!< [21..21] Start conversion of injected channels                            */
      __IOM uint32_t RGSWSTR    : 1;            /*!< [22..22] Start conversion of regular channels                             */
      __IOM uint32_t TVEN       : 1;            /*!< [23..23] Temperature sensor and VREFINT enable                            */
    } CTRL2_B;
  } ;
  
  union {
    __IOM uint32_t SMPT1;                       /*!< (@ 0x0000000C) sample time register 1                                     */
    
    struct {
      __IOM uint32_t SMPT10     : 3;            /*!< [2..0] Channel 10 sample time selection                                   */
      __IOM uint32_t SMPT11     : 3;            /*!< [5..3] Channel 11 sample time selection                                   */
      __IOM uint32_t SMPT12     : 3;            /*!< [8..6] Channel 12 sample time selection                                   */
      __IOM uint32_t SMPT13     : 3;            /*!< [11..9] Channel 13 sample time selection                                  */
      __IOM uint32_t SMPT14     : 3;            /*!< [14..12] Channel 14 sample time selection                                 */
      __IOM uint32_t SMPT15     : 3;            /*!< [17..15] Channel 15 sample time selection                                 */
      __IOM uint32_t SMPT16     : 3;            /*!< [20..18] Channel 16 sample time selection                                 */
      __IOM uint32_t SMPT17     : 3;            /*!< [23..21] Channel 17 sample time selection                                 */
    } SMPT1_B;
  } ;
  
  union {
    __IOM uint32_t SMPT2;                       /*!< (@ 0x00000010) sample time register 2                                     */
    
    struct {
      __IOM uint32_t SMPT0      : 3;            /*!< [2..0] Channel 0 sample time selection                                    */
      __IOM uint32_t SMPT1      : 3;            /*!< [5..3] Channel 1 sample time selection                                    */
      __IOM uint32_t SMPT2      : 3;            /*!< [8..6] Channel 2 sample time selection                                    */
      __IOM uint32_t SMPT3      : 3;            /*!< [11..9] Channel 3 sample time selection                                   */
      __IOM uint32_t SMPT4      : 3;            /*!< [14..12] Channel 4 sample time selection                                  */
      __IOM uint32_t SMPT5      : 3;            /*!< [17..15] Channel 5 sample time selection                                  */
      __IOM uint32_t SMPT6      : 3;            /*!< [20..18] Channel 6 sample time selection                                  */
      __IOM uint32_t SMPT7      : 3;            /*!< [23..21] Channel 7 sample time selection                                  */
      __IOM uint32_t SMPT8      : 3;            /*!< [26..24] Channel 8 sample time selection                                  */
      __IOM uint32_t SMPT9      : 3;            /*!< [29..27] Channel 9 sample time selection                                  */
    } SMPT2_B;
  } ;
  
  union {
    __IOM uint32_t IJOF1;                       /*!< (@ 0x00000014) injected channel data offset register x                    */
    
    struct {
      __IOM uint32_t OFFSET1    : 12;           /*!< [11..0] Data offset for injected channel x                                */
    } IJOF1_B;
  } ;
  
  union {
    __IOM uint32_t IJOF2;                       /*!< (@ 0x00000018) injected channel data offset register x                    */
    
    struct {
      __IOM uint32_t OFFSET2    : 12;           /*!< [11..0] Data offset for injected channel x                                */
    } IJOF2_B;
  } ;
  
  union {
    __IOM uint32_t IJOF3;                       /*!< (@ 0x0000001C) injected channel data offset register x                    */
    
    struct {
      __IOM uint32_t OFFSET3    : 12;           /*!< [11..0] Data offset for injected channel x                                */
    } IJOF3_B;
  } ;
  
  union {
    __IOM uint32_t IJOF4;                       /*!< (@ 0x00000020) injected channel data offset register x                    */
    
    struct {
      __IOM uint32_t OFFSET4    : 12;           /*!< [11..0] Data offset for injected channel x                                */
    } IJOF4_B;
  } ;
  
  union {
    __IOM uint32_t AWDHT;                       /*!< (@ 0x00000024) watchdog higher threshold register                         */
    
    struct {
      __IOM uint32_t AWDHT      : 12;           /*!< [11..0] Analog watchdog higher threshold                                  */
    } AWDHT_B;
  } ;
  
  union {
    __IOM uint32_t AWDLT;                       /*!< (@ 0x00000028) watchdog lower threshold register                          */
    
    struct {
      __IOM uint32_t AWDLT      : 12;           /*!< [11..0] Analog watchdog lower threshold                                   */
    } AWDLT_B;
  } ;
  
  union {
    __IOM uint32_t RGSQ1;                       /*!< (@ 0x0000002C) regular sequence register 1                                */
    
    struct {
      __IOM uint32_t RGSQ13     : 5;            /*!< [4..0] 13th conversion in regular sequence                                */
      __IOM uint32_t RGSQ14     : 5;            /*!< [9..5] 14th conversion in regular sequence                                */
      __IOM uint32_t RGSQ15     : 5;            /*!< [14..10] 15th conversion in regular sequence                              */
      __IOM uint32_t RGSQ16     : 5;            /*!< [19..15] 16th conversion in regular sequence                              */
      __IOM uint32_t RGSL       : 4;            /*!< [23..20] Regular channel sequence length                                  */
    } RGSQ1_B;
  } ;
  
  union {
    __IOM uint32_t RGSQ2;                       /*!< (@ 0x00000030) regular sequence register 2                                */
    
    struct {
      __IOM uint32_t RGSQ7      : 5;            /*!< [4..0] 7th conversion in regular sequence                                 */
      __IOM uint32_t RGSQ8      : 5;            /*!< [9..5] 8th conversion in regular sequence                                 */
      __IOM uint32_t RGSQ9      : 5;            /*!< [14..10] 9th conversion in regular sequence                               */
      __IOM uint32_t RGSQ10     : 5;            /*!< [19..15] 10th conversion in regular sequence                              */
      __IOM uint32_t RGSQ11     : 5;            /*!< [24..20] 11th conversion in regular sequence                              */
      __IOM uint32_t RGSQ12     : 5;            /*!< [29..25] 12th conversion in regular sequence                              */
    } RGSQ2_B;
  } ;
  
  union {
    __IOM uint32_t RGSQ3;                       /*!< (@ 0x00000034) regular sequence register 3                                */
    
    struct {
      __IOM uint32_t RGSQ1      : 5;            /*!< [4..0] 1st conversion in regular sequence                                 */
      __IOM uint32_t RGSQ2      : 5;            /*!< [9..5] 2nd conversion in regular sequence                                 */
      __IOM uint32_t RGSQ3      : 5;            /*!< [14..10] 3rd conversion in regular sequence                               */
      __IOM uint32_t RGSQ4      : 5;            /*!< [19..15] 4th conversion in regular sequence                               */
      __IOM uint32_t RGSQ5      : 5;            /*!< [24..20] 5th conversion in regular sequence                               */
      __IOM uint32_t RGSQ6      : 5;            /*!< [29..25] 6th conversion in regular sequence                               */
    } RGSQ3_B;
  } ;
  
  union {
    __IOM uint32_t IJSQ;                        /*!< (@ 0x00000038) injected sequence register                                 */
    
    struct {
      __IOM uint32_t IJSQ1      : 5;            /*!< [4..0] 1st conversion in injected sequence                                */
      __IOM uint32_t IJSQ2      : 5;            /*!< [9..5] 2nd conversion in injected sequence                                */
      __IOM uint32_t IJSQ3      : 5;            /*!< [14..10] 3rd conversion in injected sequence                              */
      __IOM uint32_t IJSQ4      : 5;            /*!< [19..15] 4th conversion in injected sequence                              */
      __IOM uint32_t IJSL       : 2;            /*!< [21..20] Injected sequence length                                         */
    } IJSQ_B;
  } ;
  
  union {
    __IM  uint32_t IJD1;                        /*!< (@ 0x0000003C) injected data register x                                   */
    
    struct {
      __IM  uint32_t IJD1        : 16;           /*!< [15..0] Injected data                                                     */
    } IJD1_B;
  } ;
  
  union {
    __IM  uint32_t IJD2;                        /*!< (@ 0x00000040) injected data register x                                   */
    
    struct {
      __IM  uint32_t IJD2        : 16;           /*!< [15..0] Injected data                                                     */
    } IJD2_B;
  } ;
  
  union {
    __IM  uint32_t IJD3;                        /*!< (@ 0x00000044) injected data register x                                   */
    
    struct {
      __IM  uint32_t IJD3        : 16;           /*!< [15..0] Injected data                                                     */
    } IJD3_B;
  } ;
  
  union {
    __IM  uint32_t IJD4;                        /*!< (@ 0x00000048) injected data register x                                   */
    
    struct {
      __IM  uint32_t IJD4        : 16;           /*!< [15..0] Injected data                                                     */
    } IJD4_B;
  } ;
  union {
    __IM  uint32_t RDG;                       /*!< (@ 0x0000004C) regular data register                                      */
    
    struct {
      __IM  uint32_t RDATA      : 16;           /*!< [15..0] Regular data                                                      */
      __IM  uint32_t ADC2DATA   : 16;           /*!< [31..16] ADC2 data                                                        */
    } RDG_B;
  } ;
} ADC_T;                                    /*!< Size = 80 (0x50)                                                          */

/**
  * @brief General purpose I/O (GPIO)
  */

typedef struct {                                /*!< (@ 0x40010800) GPIOA Structure                                            */
  
  union {
    __IOM uint32_t CTRL0;                       /*!< (@ 0x00000000) Port configuration register 0 (GPIOn_CTRL0)                */
    
    struct {
      __IOM uint32_t MOD0       : 2;            /*!< [1..0] Port n.0 mode bits                                                 */
      __IOM uint32_t CFG0       : 2;            /*!< [3..2] Port n.0 configuration bits                                        */
      __IOM uint32_t MOD1       : 2;            /*!< [5..4] Port n.1 mode bits                                                 */
      __IOM uint32_t CFG1       : 2;            /*!< [7..6] Port n.1 configuration bits                                        */
      __IOM uint32_t MOD2       : 2;            /*!< [9..8] Port n.2 mode bits                                                 */
      __IOM uint32_t CFG2       : 2;            /*!< [11..10] Port n.2 configuration bits                                      */
      __IOM uint32_t MOD3       : 2;            /*!< [13..12] Port n.3 mode bits                                               */
      __IOM uint32_t CFG3       : 2;            /*!< [15..14] Port n.3 configuration bits                                      */
      __IOM uint32_t MOD4       : 2;            /*!< [17..16] Port n.4 mode bits                                               */
      __IOM uint32_t CFG4       : 2;            /*!< [19..18] Port n.4 configuration bits                                      */
      __IOM uint32_t MOD5       : 2;            /*!< [21..20] Port n.5 mode bits                                               */
      __IOM uint32_t CFG5       : 2;            /*!< [23..22] Port n.5 configuration bits                                      */
      __IOM uint32_t MOD6       : 2;            /*!< [25..24] Port n.6 mode bits                                               */
      __IOM uint32_t CFG6       : 2;            /*!< [27..26] Port n.6 configuration bits                                      */
      __IOM uint32_t MOD7       : 2;            /*!< [29..28] Port n.7 mode bits                                               */
      __IOM uint32_t CFG7       : 2;            /*!< [31..30] Port n.7 configuration bits                                      */
    } CTRL0_B;
  } ;
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000004) Port configuration register 1 (GPIOn_CTRL1)                */
    
    struct {
      __IOM uint32_t MOD8       : 2;            /*!< [1..0] Port n.8 mode bits                                                 */
      __IOM uint32_t CFG8       : 2;            /*!< [3..2] Port n.8 configuration bits                                        */
      __IOM uint32_t MOD9       : 2;            /*!< [5..4] Port n.9 mode bits                                                 */
      __IOM uint32_t CFG9       : 2;            /*!< [7..6] Port n.9 configuration bits                                        */
      __IOM uint32_t MOD10      : 2;            /*!< [9..8] Port n.10 mode bits                                                */
      __IOM uint32_t CFG10      : 2;            /*!< [11..10] Port n.10 configuration bits                                     */
      __IOM uint32_t MOD11      : 2;            /*!< [13..12] Port n.11 mode bits                                              */
      __IOM uint32_t CFG11      : 2;            /*!< [15..14] Port n.11 configuration bits                                     */
      __IOM uint32_t MOD12      : 2;            /*!< [17..16] Port n.12 mode bits                                              */
      __IOM uint32_t CFG12      : 2;            /*!< [19..18] Port n.12 configuration bits                                     */
      __IOM uint32_t MOD13      : 2;            /*!< [21..20] Port n.13 mode bits                                              */
      __IOM uint32_t CFG13      : 2;            /*!< [23..22] Port n.13 configuration bits                                     */
      __IOM uint32_t MOD14      : 2;            /*!< [25..24] Port n.14 mode bits                                              */
      __IOM uint32_t CFG14      : 2;            /*!< [27..26] Port n.14 configuration bits                                     */
      __IOM uint32_t MOD15      : 2;            /*!< [29..28] Port n.15 mode bits                                              */
      __IOM uint32_t CFG15      : 2;            /*!< [31..30] Port n.15 configuration bits                                     */
    } CTRL1_B;
  } ;
  
  union {
    __IM  uint32_t DIN;                         /*!< (@ 0x00000008) Port input data register (GPIOn_DIN)                       */
    
    struct {
      __IM  uint32_t DIN0       : 1;            /*!< [0..0] Port input data                                                    */
      __IM  uint32_t DIN1       : 1;            /*!< [1..1] Port input data                                                    */
      __IM  uint32_t DIN2       : 1;            /*!< [2..2] Port input data                                                    */
      __IM  uint32_t DIN3       : 1;            /*!< [3..3] Port input data                                                    */
      __IM  uint32_t DIN4       : 1;            /*!< [4..4] Port input data                                                    */
      __IM  uint32_t DIN5       : 1;            /*!< [5..5] Port input data                                                    */
      __IM  uint32_t DIN6       : 1;            /*!< [6..6] Port input data                                                    */
      __IM  uint32_t DIN7       : 1;            /*!< [7..7] Port input data                                                    */
      __IM  uint32_t DIN8       : 1;            /*!< [8..8] Port input data                                                    */
      __IM  uint32_t DIN9       : 1;            /*!< [9..9] Port input data                                                    */
      __IM  uint32_t DIN10      : 1;            /*!< [10..10] Port input data                                                  */
      __IM  uint32_t DIN11      : 1;            /*!< [11..11] Port input data                                                  */
      __IM  uint32_t DIN12      : 1;            /*!< [12..12] Port input data                                                  */
      __IM  uint32_t DIN13      : 1;            /*!< [13..13] Port input data                                                  */
      __IM  uint32_t DIN14      : 1;            /*!< [14..14] Port input data                                                  */
      __IM  uint32_t DIN15      : 1;            /*!< [15..15] Port input data                                                  */
    } DIN_B;
  } ;
  
  union {
    __IOM uint32_t DOUT;                        /*!< (@ 0x0000000C) Port output data register (GPIOn_DOUT)                     */
    
    struct {
      __IOM uint32_t DOUT0      : 1;            /*!< [0..0] Port output data                                                   */
      __IOM uint32_t DOUT1      : 1;            /*!< [1..1] Port output data                                                   */
      __IOM uint32_t DOUT2      : 1;            /*!< [2..2] Port output data                                                   */
      __IOM uint32_t DOUT3      : 1;            /*!< [3..3] Port output data                                                   */
      __IOM uint32_t DOUT4      : 1;            /*!< [4..4] Port output data                                                   */
      __IOM uint32_t DOUT5      : 1;            /*!< [5..5] Port output data                                                   */
      __IOM uint32_t DOUT6      : 1;            /*!< [6..6] Port output data                                                   */
      __IOM uint32_t DOUT7      : 1;            /*!< [7..7] Port output data                                                   */
      __IOM uint32_t DOUT8      : 1;            /*!< [8..8] Port output data                                                   */
      __IOM uint32_t DOUT9      : 1;            /*!< [9..9] Port output data                                                   */
      __IOM uint32_t DOUT10     : 1;            /*!< [10..10] Port output data                                                 */
      __IOM uint32_t DOUT11     : 1;            /*!< [11..11] Port output data                                                 */
      __IOM uint32_t DOUT12     : 1;            /*!< [12..12] Port output data                                                 */
      __IOM uint32_t DOUT13     : 1;            /*!< [13..13] Port output data                                                 */
      __IOM uint32_t DOUT14     : 1;            /*!< [14..14] Port output data                                                 */
      __IOM uint32_t DOUT15     : 1;            /*!< [15..15] Port output data                                                 */
    } DOUT_B;
  } ;
  
  union {
    __OM  uint32_t BSC;                         /*!< (@ 0x00000010) Port bit set/reset register (GPIOn_BSC)                    */
    
    struct {
      __OM  uint32_t BS0        : 1;            /*!< [0..0] Set bit 0                                                          */
      __OM  uint32_t BS1        : 1;            /*!< [1..1] Set bit 1                                                          */
      __OM  uint32_t BS2        : 1;            /*!< [2..2] Set bit 1                                                          */
      __OM  uint32_t BS3        : 1;            /*!< [3..3] Set bit 3                                                          */
      __OM  uint32_t BS4        : 1;            /*!< [4..4] Set bit 4                                                          */
      __OM  uint32_t BS5        : 1;            /*!< [5..5] Set bit 5                                                          */
      __OM  uint32_t BS6        : 1;            /*!< [6..6] Set bit 6                                                          */
      __OM  uint32_t BS7        : 1;            /*!< [7..7] Set bit 7                                                          */
      __OM  uint32_t BS8        : 1;            /*!< [8..8] Set bit 8                                                          */
      __OM  uint32_t BS9        : 1;            /*!< [9..9] Set bit 9                                                          */
      __OM  uint32_t BS10       : 1;            /*!< [10..10] Set bit 10                                                       */
      __OM  uint32_t BS11       : 1;            /*!< [11..11] Set bit 11                                                       */
      __OM  uint32_t BS12       : 1;            /*!< [12..12] Set bit 12                                                       */
      __OM  uint32_t BS13       : 1;            /*!< [13..13] Set bit 13                                                       */
      __OM  uint32_t BS14       : 1;            /*!< [14..14] Set bit 14                                                       */
      __OM  uint32_t BS15       : 1;            /*!< [15..15] Set bit 15                                                       */
      __OM  uint32_t BC0        : 1;            /*!< [16..16] Clear bit 0                                                      */
      __OM  uint32_t BC1        : 1;            /*!< [17..17] Clear bit 1                                                      */
      __OM  uint32_t BC2        : 1;            /*!< [18..18] Clear bit 2                                                      */
      __OM  uint32_t BC3        : 1;            /*!< [19..19] Clear bit 3                                                      */
      __OM  uint32_t BC4        : 1;            /*!< [20..20] Clear bit 4                                                      */
      __OM  uint32_t BC5        : 1;            /*!< [21..21] Clear bit 5                                                      */
      __OM  uint32_t BC6        : 1;            /*!< [22..22] Clear bit 6                                                      */
      __OM  uint32_t BC7        : 1;            /*!< [23..23] Clear bit 7                                                      */
      __OM  uint32_t BC8        : 1;            /*!< [24..24] Clear bit 8                                                      */
      __OM  uint32_t BC9        : 1;            /*!< [25..25] Clear bit 9                                                      */
      __OM  uint32_t BC10       : 1;            /*!< [26..26] Clear bit 10                                                     */
      __OM  uint32_t BC11       : 1;            /*!< [27..27] Clear bit 11                                                     */
      __OM  uint32_t BC12       : 1;            /*!< [28..28] Clear bit 12                                                     */
      __OM  uint32_t BC13       : 1;            /*!< [29..29] Clear bit 13                                                     */
      __OM  uint32_t BC14       : 1;            /*!< [30..30] Clear bit 14                                                     */
      __OM  uint32_t BC15       : 1;            /*!< [31..31] Clear bit 15                                                     */
    } BSC_B;
  } ;
  
  union {
    __OM  uint32_t BC;                          /*!< (@ 0x00000014) Port bit clear register (GPIOn_BC)                         */
    
    struct {
      __OM  uint32_t BC0        : 1;            /*!< [0..0] Clear bit 0                                                        */
      __OM  uint32_t BC1        : 1;            /*!< [1..1] Clear bit 1                                                        */
      __OM  uint32_t BC2        : 1;            /*!< [2..2] Clear bit 1                                                        */
      __OM  uint32_t BC3        : 1;            /*!< [3..3] Clear bit 3                                                        */
      __OM  uint32_t BC4        : 1;            /*!< [4..4] Clear bit 4                                                        */
      __OM  uint32_t BC5        : 1;            /*!< [5..5] Clear bit 5                                                        */
      __OM  uint32_t BC6        : 1;            /*!< [6..6] Clear bit 6                                                        */
      __OM  uint32_t BC7        : 1;            /*!< [7..7] Clear bit 7                                                        */
      __OM  uint32_t BC8        : 1;            /*!< [8..8] Clear bit 8                                                        */
      __OM  uint32_t BC9        : 1;            /*!< [9..9] Clear bit 9                                                        */
      __OM  uint32_t BC10       : 1;            /*!< [10..10] Clear bit 10                                                     */
      __OM  uint32_t BC11       : 1;            /*!< [11..11] Clear bit 11                                                     */
      __OM  uint32_t BC12       : 1;            /*!< [12..12] Clear bit 12                                                     */
      __OM  uint32_t BC13       : 1;            /*!< [13..13] Clear bit 13                                                     */
      __OM  uint32_t BC14       : 1;            /*!< [14..14] Clear bit 14                                                     */
      __OM  uint32_t BC15       : 1;            /*!< [15..15] Clear bit 15                                                     */
    } BC_B;
  } ;
  
  union {
    __IOM uint32_t LOCK;                        /*!< (@ 0x00000018) Port configuration lock register (GPIOn_LOCK)              */
    
    struct {
      __IOM uint32_t LCK0       : 1;            /*!< [0..0] Port A Lock bit 0                                                  */
      __IOM uint32_t LCK1       : 1;            /*!< [1..1] Port A Lock bit 1                                                  */
      __IOM uint32_t LCK2       : 1;            /*!< [2..2] Port A Lock bit 2                                                  */
      __IOM uint32_t LCK3       : 1;            /*!< [3..3] Port A Lock bit 3                                                  */
      __IOM uint32_t LCK4       : 1;            /*!< [4..4] Port A Lock bit 4                                                  */
      __IOM uint32_t LCK5       : 1;            /*!< [5..5] Port A Lock bit 5                                                  */
      __IOM uint32_t LCK6       : 1;            /*!< [6..6] Port A Lock bit 6                                                  */
      __IOM uint32_t LCK7       : 1;            /*!< [7..7] Port A Lock bit 7                                                  */
      __IOM uint32_t LCK8       : 1;            /*!< [8..8] Port A Lock bit 8                                                  */
      __IOM uint32_t LCK9       : 1;            /*!< [9..9] Port A Lock bit 9                                                  */
      __IOM uint32_t LCK10      : 1;            /*!< [10..10] Port A Lock bit 10                                               */
      __IOM uint32_t LCK11      : 1;            /*!< [11..11] Port A Lock bit 11                                               */
      __IOM uint32_t LCK12      : 1;            /*!< [12..12] Port A Lock bit 12                                               */
      __IOM uint32_t LCK13      : 1;            /*!< [13..13] Port A Lock bit 13                                               */
      __IOM uint32_t LCK14      : 1;            /*!< [14..14] Port A Lock bit 14                                               */
      __IOM uint32_t LCK15      : 1;            /*!< [15..15] Port A Lock bit 15                                               */
      __IOM uint32_t LCKK       : 1;            /*!< [16..16] Lock key                                                         */
    } LOCK_B;
  } ;
} GPIO_T;                                   /*!< Size = 28 (0x1c)                                                          */

/**
  * @brief External Interrupt (EINT)
  */

typedef struct {                                /*!< (@ 0x40010400) EINT Structure                                             */
  
  union {
    __IOM uint32_t IEN;                         /*!< (@ 0x00000000) Interrupt mask register (EINT_IMR)                         */
    
    struct {
      __IOM uint32_t IEN0       : 1;            /*!< [0..0] Interrupt Mask on line 0                                           */
      __IOM uint32_t IEN1       : 1;            /*!< [1..1] Interrupt Mask on line 1                                           */
      __IOM uint32_t IEN2       : 1;            /*!< [2..2] Interrupt Mask on line 2                                           */
      __IOM uint32_t IEN3       : 1;            /*!< [3..3] Interrupt Mask on line 3                                           */
      __IOM uint32_t IEN4       : 1;            /*!< [4..4] Interrupt Mask on line 4                                           */
      __IOM uint32_t IEN5       : 1;            /*!< [5..5] Interrupt Mask on line 5                                           */
      __IOM uint32_t IEN6       : 1;            /*!< [6..6] Interrupt Mask on line 6                                           */
      __IOM uint32_t IEN7       : 1;            /*!< [7..7] Interrupt Mask on line 7                                           */
      __IOM uint32_t IEN8       : 1;            /*!< [8..8] Interrupt Mask on line 8                                           */
      __IOM uint32_t IEN9       : 1;            /*!< [9..9] Interrupt Mask on line 9                                           */
      __IOM uint32_t IEN10      : 1;            /*!< [10..10] Interrupt Mask on line 10                                        */
      __IOM uint32_t IEN11      : 1;            /*!< [11..11] Interrupt Mask on line 11                                        */
      __IOM uint32_t IEN12      : 1;            /*!< [12..12] Interrupt Mask on line 12                                        */
      __IOM uint32_t IEN13      : 1;            /*!< [13..13] Interrupt Mask on line 13                                        */
      __IOM uint32_t IEN14      : 1;            /*!< [14..14] Interrupt Mask on line 14                                        */
      __IOM uint32_t IEN15      : 1;            /*!< [15..15] Interrupt Mask on line 15                                        */
      __IOM uint32_t IEN16      : 1;            /*!< [16..16] Interrupt Mask on line 16                                        */
      __IOM uint32_t IEN17      : 1;            /*!< [17..17] Interrupt Mask on line 17                                        */
      __IOM uint32_t IEN18      : 1;            /*!< [18..18] Interrupt Mask on line 18                                        */
      __IOM uint32_t IEN19      : 1;            /*!< [19..19] Interrupt Mask on line 19                                        */
    } IEN_B;
  } ;
  
  union {
    __IOM uint32_t EEN;                         /*!< (@ 0x00000004) Event mask register (EINT_EMR)                             */
    
    struct {
      __IOM uint32_t EEN0       : 1;            /*!< [0..0] Event Mask on line 0                                               */
      __IOM uint32_t EEN1       : 1;            /*!< [1..1] Event Mask on line 1                                               */
      __IOM uint32_t EEN2       : 1;            /*!< [2..2] Event Mask on line 2                                               */
      __IOM uint32_t EEN3       : 1;            /*!< [3..3] Event Mask on line 3                                               */
      __IOM uint32_t EEN4       : 1;            /*!< [4..4] Event Mask on line 4                                               */
      __IOM uint32_t EEN5       : 1;            /*!< [5..5] Event Mask on line 5                                               */
      __IOM uint32_t EEN6       : 1;            /*!< [6..6] Event Mask on line 6                                               */
      __IOM uint32_t EEN7       : 1;            /*!< [7..7] Event Mask on line 7                                               */
      __IOM uint32_t EEN8       : 1;            /*!< [8..8] Event Mask on line 8                                               */
      __IOM uint32_t EEN9       : 1;            /*!< [9..9] Event Mask on line 9                                               */
      __IOM uint32_t EEN10      : 1;            /*!< [10..10] Event Mask on line 10                                            */
      __IOM uint32_t EEN11      : 1;            /*!< [11..11] Event Mask on line 11                                            */
      __IOM uint32_t EEN12      : 1;            /*!< [12..12] Event Mask on line 12                                            */
      __IOM uint32_t EEN13      : 1;            /*!< [13..13] Event Mask on line 13                                            */
      __IOM uint32_t EEN14      : 1;            /*!< [14..14] Event Mask on line 14                                            */
      __IOM uint32_t EEN15      : 1;            /*!< [15..15] Event Mask on line 15                                            */
      __IOM uint32_t EEN16      : 1;            /*!< [16..16] Event Mask on line 16                                            */
      __IOM uint32_t EEN17      : 1;            /*!< [17..17] Event Mask on line 17                                            */
      __IOM uint32_t EEN18      : 1;            /*!< [18..18] Event Mask on line 18                                            */
      __IOM uint32_t EEN19      : 1;            /*!< [19..19] Event Mask on line 19                                            */
    } EEN_B;
  } ;
  
  union {
    __IOM uint32_t RTEN;                        /*!< (@ 0x00000008) Rising Trigger selection register (EINT_RTSR)              */
    
    struct {
      __IOM uint32_t RT0        : 1;            /*!< [0..0] Rising trigger event configuration of line 0                       */
      __IOM uint32_t RT1        : 1;            /*!< [1..1] Rising trigger event configuration of line 1                       */
      __IOM uint32_t RT2        : 1;            /*!< [2..2] Rising trigger event configuration of line 2                       */
      __IOM uint32_t RT3        : 1;            /*!< [3..3] Rising trigger event configuration of line 3                       */
      __IOM uint32_t RT4        : 1;            /*!< [4..4] Rising trigger event configuration of line 4                       */
      __IOM uint32_t RT5        : 1;            /*!< [5..5] Rising trigger event configuration of line 5                       */
      __IOM uint32_t RT6        : 1;            /*!< [6..6] Rising trigger event configuration of line 6                       */
      __IOM uint32_t RT7        : 1;            /*!< [7..7] Rising trigger event configuration of line 7                       */
      __IOM uint32_t RT8        : 1;            /*!< [8..8] Rising trigger event configuration of line 8                       */
      __IOM uint32_t RT9        : 1;            /*!< [9..9] Rising trigger event configuration of line 9                       */
      __IOM uint32_t RT10       : 1;            /*!< [10..10] Rising trigger event configuration of line 10                    */
      __IOM uint32_t RT11       : 1;            /*!< [11..11] Rising trigger event configuration of line 11                    */
      __IOM uint32_t RT12       : 1;            /*!< [12..12] Rising trigger event configuration of line 12                    */
      __IOM uint32_t RT13       : 1;            /*!< [13..13] Rising trigger event configuration of line 13                    */
      __IOM uint32_t RT14       : 1;            /*!< [14..14] Rising trigger event configuration of line 14                    */
      __IOM uint32_t RT15       : 1;            /*!< [15..15] Rising trigger event configuration of line 15                    */
      __IOM uint32_t RT16       : 1;            /*!< [16..16] Rising trigger event configuration of line 16                    */
      __IOM uint32_t RT17       : 1;            /*!< [17..17] Rising trigger event configuration of line 17                    */
      __IOM uint32_t RT18       : 1;            /*!< [18..18] Rising trigger event configuration of line 18                    */
      __IOM uint32_t RT19       : 1;            /*!< [19..19] Rising trigger event configuration of line 19                    */
    } RTEN_B;
  } ;
  
  union {
    __IOM uint32_t FTEN;                        /*!< (@ 0x0000000C) Falling Trigger selection register (EINT_FTSR)             */
    
    struct {
      __IOM uint32_t FT0        : 1;            /*!< [0..0] Falling trigger event configuration of line 0                      */
      __IOM uint32_t FT1        : 1;            /*!< [1..1] Falling trigger event configuration of line 1                      */
      __IOM uint32_t FT2        : 1;            /*!< [2..2] Falling trigger event configuration of line 2                      */
      __IOM uint32_t FT3        : 1;            /*!< [3..3] Falling trigger event configuration of line 3                      */
      __IOM uint32_t FT4        : 1;            /*!< [4..4] Falling trigger event configuration of line 4                      */
      __IOM uint32_t FT5        : 1;            /*!< [5..5] Falling trigger event configuration of line 5                      */
      __IOM uint32_t FT6        : 1;            /*!< [6..6] Falling trigger event configuration of line 6                      */
      __IOM uint32_t FT7        : 1;            /*!< [7..7] Falling trigger event configuration of line 7                      */
      __IOM uint32_t FT8        : 1;            /*!< [8..8] Falling trigger event configuration of line 8                      */
      __IOM uint32_t FT9        : 1;            /*!< [9..9] Falling trigger event configuration of line 9                      */
      __IOM uint32_t FT10       : 1;            /*!< [10..10] Falling trigger event configuration of line 10                   */
      __IOM uint32_t FT11       : 1;            /*!< [11..11] Falling trigger event configuration of line 11                   */
      __IOM uint32_t FT12       : 1;            /*!< [12..12] Falling trigger event configuration of line 12                   */
      __IOM uint32_t FT13       : 1;            /*!< [13..13] Falling trigger event configuration of line 13                   */
      __IOM uint32_t FT14       : 1;            /*!< [14..14] Falling trigger event configuration of line 14                   */
      __IOM uint32_t FT15       : 1;            /*!< [15..15] Falling trigger event configuration of line 15                   */
      __IOM uint32_t FT16       : 1;            /*!< [16..16] Falling trigger event configuration of line 16                   */
      __IOM uint32_t FT17       : 1;            /*!< [17..17] Falling trigger event configuration of line 17                   */
      __IOM uint32_t FT18       : 1;            /*!< [18..18] Falling trigger event configuration of line 18                   */
      __IOM uint32_t FT19       : 1;            /*!< [19..19] Falling trigger event configuration of line 19                   */
    } FTEN_B;
  } ;
  
  union {
    __IOM uint32_t SWIEN;                       /*!< (@ 0x00000010) Software interrupt event register (EINT_SWIER)             */
    
    struct {
      __IOM uint32_t SWIEN0     : 1;            /*!< [0..0] Software Interrupt on line 0                                       */
      __IOM uint32_t SWIEN1     : 1;            /*!< [1..1] Software Interrupt on line 1                                       */
      __IOM uint32_t SWIEN2     : 1;            /*!< [2..2] Software Interrupt on line 2                                       */
      __IOM uint32_t SWIEN3     : 1;            /*!< [3..3] Software Interrupt on line 3                                       */
      __IOM uint32_t SWIEN4     : 1;            /*!< [4..4] Software Interrupt on line 4                                       */
      __IOM uint32_t SWIEN5     : 1;            /*!< [5..5] Software Interrupt on line 5                                       */
      __IOM uint32_t SWIEN6     : 1;            /*!< [6..6] Software Interrupt on line 6                                       */
      __IOM uint32_t SWIEN7     : 1;            /*!< [7..7] Software Interrupt on line 7                                       */
      __IOM uint32_t SWIEN8     : 1;            /*!< [8..8] Software Interrupt on line 8                                       */
      __IOM uint32_t SWIEN9     : 1;            /*!< [9..9] Software Interrupt on line 9                                       */
      __IOM uint32_t SWIEN10    : 1;            /*!< [10..10] Software Interrupt on line 10                                    */
      __IOM uint32_t SWIEN11    : 1;            /*!< [11..11] Software Interrupt on line 11                                    */
      __IOM uint32_t SWIEN12    : 1;            /*!< [12..12] Software Interrupt on line 12                                    */
      __IOM uint32_t SWIEN13    : 1;            /*!< [13..13] Software Interrupt on line 13                                    */
      __IOM uint32_t SWIEN14    : 1;            /*!< [14..14] Software Interrupt on line 14                                    */
      __IOM uint32_t SWIEN15    : 1;            /*!< [15..15] Software Interrupt on line 15                                    */
      __IOM uint32_t SWIEN16    : 1;            /*!< [16..16] Software Interrupt on line 16                                    */
      __IOM uint32_t SWIEN17    : 1;            /*!< [17..17] Software Interrupt on line 17                                    */
      __IOM uint32_t SWIEN18    : 1;            /*!< [18..18] Software Interrupt on line 18                                    */
      __IOM uint32_t SWIEN19    : 1;            /*!< [19..19] Software Interrupt on line 19                                    */
    } SWIEN_B;
  } ;
  
  union {
    __IOM uint32_t IF;                          /*!< (@ 0x00000014) Interrupt Flag Enable register (EINT_IF)                   */
    
    struct {
      __IOM uint32_t IF0        : 1;            /*!< [0..0] Pending bit 0                                                      */
      __IOM uint32_t IF1        : 1;            /*!< [1..1] Pending bit 1                                                      */
      __IOM uint32_t IF2        : 1;            /*!< [2..2] Pending bit 2                                                      */
      __IOM uint32_t IF3        : 1;            /*!< [3..3] Pending bit 3                                                      */
      __IOM uint32_t IF4        : 1;            /*!< [4..4] Pending bit 4                                                      */
      __IOM uint32_t IF5        : 1;            /*!< [5..5] Pending bit 5                                                      */
      __IOM uint32_t IF6        : 1;            /*!< [6..6] Pending bit 6                                                      */
      __IOM uint32_t IF7        : 1;            /*!< [7..7] Pending bit 7                                                      */
      __IOM uint32_t IF8        : 1;            /*!< [8..8] Pending bit 8                                                      */
      __IOM uint32_t IF9        : 1;            /*!< [9..9] Pending bit 9                                                      */
      __IOM uint32_t IF10       : 1;            /*!< [10..10] Pending bit 10                                                   */
      __IOM uint32_t IF11       : 1;            /*!< [11..11] Pending bit 11                                                   */
      __IOM uint32_t IF12       : 1;            /*!< [12..12] Pending bit 12                                                   */
      __IOM uint32_t IF13       : 1;            /*!< [13..13] Pending bit 13                                                   */
      __IOM uint32_t IF14       : 1;            /*!< [14..14] Pending bit 14                                                   */
      __IOM uint32_t IF15       : 1;            /*!< [15..15] Pending bit 15                                                   */
      __IOM uint32_t IF16       : 1;            /*!< [16..16] Pending bit 16                                                   */
      __IOM uint32_t IF17       : 1;            /*!< [17..17] Pending bit 17                                                   */
      __IOM uint32_t IF18       : 1;            /*!< [18..18] Pending bit 18                                                   */
      __IOM uint32_t IF19       : 1;            /*!< [19..19] Pending bit 19                                                   */
    } IF_B;
  } ;
} EINT_T;                                    /*!< Size = 24 (0x18)                                                          */

/**
  * @brief Alternate function I/O (AFIO)
  */

typedef struct {                                /*!< (@ 0x40010000) AFIO Structure                                             */
  
  union {
    __IOM uint32_t EVCTRL;                      /*!< (@ 0x00000000) Event control register (AFIO_EVCTRL)                       */
    
    struct {
      __IOM uint32_t PINSEL     : 4;            /*!< [3..0] PINSEL                                                             */
      __IOM uint32_t PORTSEL    : 3;            /*!< [6..4] PORTSEL                                                            */
      __IOM uint32_t EVOEN      : 1;            /*!< [7..7] EVOEN                                                              */
    } EVCTRL_B;
  } ;
  
  union {
    __IOM uint32_t REMAP;                       /*!< (@ 0x00000004) Alternate function IO remap and Serial wire JTAG
                                                                    configuration register (AFIO_REMAP)                        */
    
    struct {
      __IOM uint32_t SPI1_REMAP : 1;            /*!< [0..0] SPI1 remapping                                                     */
      __IOM uint32_t I2C1_REMAP : 1;            /*!< [1..1] I2C1 remapping                                                     */
      __IOM uint32_t USART1_REMAP : 1;          /*!< [2..2] USART1 remapping                                                   */
      __IOM uint32_t USART2_REMAP : 1;          /*!< [3..3] USART2 remapping                                                   */
      __IOM uint32_t USART3_REMAP : 2;          /*!< [5..4] USART3 remapping                                                   */
      __IOM uint32_t TMR1_REMAP : 2;            /*!< [7..6] TMR1 remapping                                                     */
      __IOM uint32_t TMR2_REMAP : 2;            /*!< [9..8] TMR2 remapping                                                     */
      __IOM uint32_t TMR3_REMAP : 2;            /*!< [11..10] TMR3 remapping                                                   */
      __IOM uint32_t TMR4_REMAP : 1;            /*!< [12..12] TMR4 remapping                                                   */
      __IOM uint32_t CAN_REMAP  : 2;            /*!< [14..13] CAN alternate function remapping                                 */
      __IOM uint32_t PD01_REMAP : 1;            /*!< [15..15] Port D0/Port D1 mapping on OSC_IN/OSC_OUT                        */
      __IOM uint32_t TMR5_CH4_REMAP : 1;        /*!< [16..16] TMR5 channel4 internal remap                                     */
      __IOM uint32_t ADC1_ETI_REMAP : 1;        /*!< [17..17] ADC 1 External trigger injected conversion remapping             */
      __IOM uint32_t ADC1_ETR_REMAP : 1;        /*!< [18..18] ADC 1 external trigger regular conversion remapping              */
      __IOM uint32_t ADC2_ETI_REMAP : 1;        /*!< [19..19] ADC 2 external trigger injected conversion remapping             */
      __IOM uint32_t ADC2_ETR_REMAP : 1;        /*!< [20..20] ADC 2 external trigger regular conversion remapping              */
      __IM  uint32_t            : 3;
      __IOM uint32_t SWJ_CFG    : 3;            /*!< [26..24] Serial wire JTAG configuration                                   */
    } REMAP_B;
  } ;
  
  union {
    __IOM uint32_t EINTCFG1;                    /*!< (@ 0x00000008) External interrupt configuration register1 (AFIO_EINTCFG1) */
    
    struct {
      __IOM uint32_t EINT0      : 4;            /*!< [3..0] EINT 0 configuration                                               */
      __IOM uint32_t EINT1      : 4;            /*!< [7..4] EINT 1 configuration                                               */
      __IOM uint32_t EINT2      : 4;            /*!< [11..8] EINT 2 configuration                                              */
      __IOM uint32_t EINT3      : 4;            /*!< [15..12] EINT 3 configuration                                             */
    } EINTCFG1_B;
  } ;
  
  union {
    __IOM uint32_t EINTCFG2;                    /*!< (@ 0x0000000C) External interrupt configuration register2 (AFIO_EINTCFG2) */
    
    struct {
      __IOM uint32_t EINT4      : 4;            /*!< [3..0] EINT 4 configuration                                               */
      __IOM uint32_t EINT5      : 4;            /*!< [7..4] EINT 5 configuration                                               */
      __IOM uint32_t EINT6      : 4;            /*!< [11..8] EINT 6 configuration                                              */
      __IOM uint32_t EINT7      : 4;            /*!< [15..12] EINT 7 configuration                                             */
    } EINTCFG2_B;
  } ;
  
  union {
    __IOM uint32_t EINTCFG3;                    /*!< (@ 0x00000010) External interrupt configuration register3 (AFIO_EINTCFG3) */
    
    struct {
      __IOM uint32_t EINT8      : 4;            /*!< [3..0] EINT 8 configuration                                               */
      __IOM uint32_t EINT9      : 4;            /*!< [7..4] EINT 9 configuration                                               */
      __IOM uint32_t EINT10     : 4;            /*!< [11..8] EINT 10 configuration                                             */
      __IOM uint32_t EINT11     : 4;            /*!< [15..12] EINT 11 configuration                                            */
    } EINTCFG3_B;
  } ;
  
  union {
    __IOM uint32_t EINTCFG4;                    /*!< (@ 0x00000014) External interrupt configuration register4 (AFIO_EINTCFG4) */
    
    struct {
      __IOM uint32_t EINT12     : 4;            /*!< [3..0] EINT 12 configuration                                              */
      __IOM uint32_t EINT13     : 4;            /*!< [7..4] EINT 13 configuration                                              */
      __IOM uint32_t EINT14     : 4;            /*!< [11..8] EINT 14 configuration                                             */
      __IOM uint32_t EINT15     : 4;            /*!< [15..12] EINT 15 configuration                                            */
    } EINTCFG4_B;
  } ;
  
  union {
    __IOM uint32_t REMAP2;                      /*!< (@ 0x00000018) Alternate function IO remap register2 (AFIO_REMAP2)        */
    
    struct {
      __IM  uint32_t            : 5;
      __IOM uint32_t TMR9_REMAP : 1;            /*!< [5..5] TMR9 remapping                                                     */
      __IOM uint32_t TMR10_REMAP : 1;           /*!< [6..6] TMR10 remapping                                                    */
      __IOM uint32_t TMR11_REMAP : 1;           /*!< [7..7] TMR11 remapping                                                    */
      __IOM uint32_t TMR13_REMAP : 1;           /*!< [8..8] TMR13 remapping                                                    */
      __IOM uint32_t TMR14_REMAP : 1;           /*!< [9..9] TMR14 remapping                                                    */
      __IOM uint32_t EMMC_NADV  : 1;            /*!< [10..10] NADV connect/disconnect                                          */
    } REMAP2_B;
  } ;
} AFIO_T;                                    /*!< Size = 28 (0x1c)                                                          */

/**
  * @brief Power control (PMU)
  */

typedef struct {                                /*!< (@ 0x40007000) PMU Structure                                              */
  
  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Power control register (PMU_CTRL)                          */
    
    struct {
      __IOM uint32_t LPSM       : 1;            /*!< [0..0] Low Power Deep Sleep                                               */
      __IOM uint32_t SBMDS      : 1;            /*!< [1..1] Power Down Deep Sleep                                              */
      __IOM uint32_t RWUPF      : 1;            /*!< [2..2] Clear Wake-up Flag                                                 */
      __IOM uint32_t RSBF       : 1;            /*!< [3..3] Clear STANDBY Flag                                                 */
      __IOM uint32_t PVMEN      : 1;            /*!< [4..4] Power Voltage Detector Enable                                      */
      __IOM uint32_t PLMS       : 3;            /*!< [7..5] PVD Level Selection                                                */
      __IOM uint32_t BAKRWEN    : 1;            /*!< [8..8] Disable Bakr Domain write protection                             */
    } CTRL_B;
  } ;
  
  union {
    __IOM uint32_t CTRLF;                       /*!< (@ 0x00000004) Power control/status register (PMU_CTRLF)                  */
    
    struct {
      __IM  uint32_t WUPF       : 1;            /*!< [0..0] Wake-Up Flag                                                       */
      __IM  uint32_t SBMF       : 1;            /*!< [1..1] STANDBY Flag                                                       */
      __IM  uint32_t PVMF       : 1;            /*!< [2..2] PVD Output                                                         */
      __IM  uint32_t            : 5;
      __IOM uint32_t WUPEN      : 1;            /*!< [8..8] Enable WKUP pin                                                    */
    } CTRLF_B;
  } ;
} PMU_T;                                     /*!< Size = 8 (0x8)                                                            */

/**
  * @brief Bakr registers (BAKR)
  */

typedef struct {                                /*!< (@ 0x40006C00) BAKR Structure                                             */
    union  {
    __IM uint32_t RESERVED1;

    struct    {
      __IM uint32_t RESERVED    : 32;
    } RESERVED1_B;

  };
  
  union {
    __IOM uint32_t DATA1;                       /*!< (@ 0x00000004) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA1_B;
  } ;
  
  union {
    __IOM uint32_t DATA2;                       /*!< (@ 0x00000008) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA2_B;
  } ;
  
  union {
    __IOM uint32_t DATA3;                       /*!< (@ 0x0000000C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA3_B;
  } ;
  
  union {
    __IOM uint32_t DATA4;                       /*!< (@ 0x00000010) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA4_B;
  } ;
  
  union {
    __IOM uint32_t DATA5;                       /*!< (@ 0x00000014) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA5_B;
  } ;
  
  union {
    __IOM uint32_t DATA6;                       /*!< (@ 0x00000018) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA6_B;
  } ;
  
  union {
    __IOM uint32_t DATA7;                       /*!< (@ 0x0000001C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA7_B;
  } ;
  
  union {
    __IOM uint32_t DATA8;                       /*!< (@ 0x00000020) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA8_B;
  } ;
  
  union {
    __IOM uint32_t DATA9;                       /*!< (@ 0x00000024) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA9_B;
  } ;
  
  union {
    __IOM uint32_t DATA10;                      /*!< (@ 0x00000028) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA10_B;
  } ;
  
  union {
    __IOM uint32_t RTCCTRL;                     /*!< (@ 0x0000002C) RTC clock calibration register (BAKR_RTCCTRL)              */
    
    struct {
      __IOM uint32_t CALP       : 7;            /*!< [6..0] Calibration value                                                  */
      __IOM uint32_t RTCO       : 1;            /*!< [7..7] Calibration Clock Output                                           */
      __IOM uint32_t ASOEN      : 1;            /*!< [8..8] Alarm or second output enable                                      */
      __IOM uint32_t ASOC       : 1;            /*!< [9..9] Alarm or second output selection                                   */
    } RTCCTRL_B;
  } ;
  
  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000030) Bakr control register (BAKR_CTRL_B)                      */
    
    struct {
      __IOM uint32_t TPEN       : 1;            /*!< [0..0] Tamper pin enable                                                  */
      __IOM uint32_t TPTM       : 1;            /*!< [1..1] Tamper pin active level                                            */
    } CTRL_B;
  } ;
  
  union {
    __IOM uint32_t CTRLF;                       /*!< (@ 0x00000034) BAKR_CSR control/status register (BAKR_CTRLF)              */
    
    struct {
      __OM  uint32_t RTPEF      : 1;            /*!< [0..0] Clear Tamper event                                                 */
      __OM  uint32_t RTPIF      : 1;            /*!< [1..1] Clear Tamper Interrupt                                             */
      __IOM uint32_t TPIEN      : 1;            /*!< [2..2] Tamper Pin interrupt enable                                        */
      __IM  uint32_t            : 5;
      __IM  uint32_t TPEF       : 1;            /*!< [8..8] Tamper Event Flag                                                  */
      __IM  uint32_t TPIF       : 1;            /*!< [9..9] Tamper Interrupt Flag                                              */
    } CTRLF_B;
  } ;
  
    union  {
    __IM uint32_t RESERVED2;

    struct    {
      __IM uint32_t RESERVED    : 32;
    } RESERVED2_B;

  };

  /**
   * @brief BAKR reserve3 register
   */
  union  {
    __IM uint32_t RESERVED3;

    struct    {
      __IM uint32_t RESERVED    : 32;
    } RESERVED3_B;

  };
  
 
  union {
    __IOM uint32_t DATA11;                      /*!< (@ 0x00000040) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA11_B;
  } ;
  
  union {
    __IOM uint32_t DATA12;                      /*!< (@ 0x00000044) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA12_B;
  } ;
  
  union {
    __IOM uint32_t DATA13;                      /*!< (@ 0x00000048) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA13_B;
  } ;
  
  union {
    __IOM uint32_t DATA14;                      /*!< (@ 0x0000004C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA14_B;
  } ;
  
  union {
    __IOM uint32_t DATA15;                      /*!< (@ 0x00000050) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA15_B;
  } ;
  
  union {
    __IOM uint32_t DATA16;                      /*!< (@ 0x00000054) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA16_B;
  } ;
  
  union {
    __IOM uint32_t DATA17;                      /*!< (@ 0x00000058) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA17_B;
  } ;
  
  union {
    __IOM uint32_t DATA18;                      /*!< (@ 0x0000005C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA18_B;
  } ;
  
  union {
    __IOM uint32_t DATA19;                      /*!< (@ 0x00000060) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA19_B;
  } ;
  
  union {
    __IOM uint32_t DATA20;                      /*!< (@ 0x00000064) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA20_B;
  } ;
  
  union {
    __IOM uint32_t DATA21;                      /*!< (@ 0x00000068) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA21_B;
  } ;
  
  union {
    __IOM uint32_t DATA22;                      /*!< (@ 0x0000006C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA22_B;
  } ;
  
  union {
    __IOM uint32_t DATA23;                      /*!< (@ 0x00000070) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA23_B;
  } ;
  
  union {
    __IOM uint32_t DATA24;                      /*!< (@ 0x00000074) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA24_B;
  } ;
  
  union {
    __IOM uint32_t DATA25;                      /*!< (@ 0x00000078) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA25_B;
  } ;
  
  union {
    __IOM uint32_t DATA26;                      /*!< (@ 0x0000007C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA26_B;
  } ;
  
  union {
    __IOM uint32_t DATA27;                      /*!< (@ 0x00000080) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA27_B;
  } ;
  
  union {
    __IOM uint32_t DATA28;                      /*!< (@ 0x00000084) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA28_B;
  } ;
  
  union {
    __IOM uint32_t DATA29;                      /*!< (@ 0x00000088) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA29_B;
  } ;
  
  union {
    __IOM uint32_t DATA30;                      /*!< (@ 0x0000008C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA30_B;
  } ;
  
  union {
    __IOM uint32_t DATA31;                      /*!< (@ 0x00000090) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA31_B;
  } ;
  
  union {
    __IOM uint32_t DATA32;                      /*!< (@ 0x00000094) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA32_B;
  } ;
  
  union {
    __IOM uint32_t DATA33;                      /*!< (@ 0x00000098) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA33_B;
  } ;
  
  union {
    __IOM uint32_t DATA34;                      /*!< (@ 0x0000009C) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA34_B;
  } ;
  
  union {
    __IOM uint32_t DATA35;                      /*!< (@ 0x000000A0) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA35_B;
  } ;
  
  union {
    __IOM uint32_t DATA36;                      /*!< (@ 0x000000A4) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA36_B;
  } ;
  
  union {
    __IOM uint32_t DATA37;                      /*!< (@ 0x000000A8) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA37_B;
  } ;
  
  union {
    __IOM uint32_t DATA38;                      /*!< (@ 0x000000AC) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA38_B;
  } ;
  
  union {
    __IOM uint32_t DATA39;                      /*!< (@ 0x000000B0) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA39_B;
  } ;
  
  union {
    __IOM uint32_t DATA40;                      /*!< (@ 0x000000B4) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA40_B;
  } ;
  
  union {
    __IOM uint32_t DATA41;                      /*!< (@ 0x000000B8) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA41_B;
  } ;
  
  union {
    __IOM uint32_t DATA42;                      /*!< (@ 0x000000BC) Bakr data register (BAKR_DATA)                           */
    
    struct {
      __IOM uint32_t DATA       : 16;           /*!< [15..0] Bakr data                                                       */
    } DATA42_B;
  } ;
} BAKR_T;                                    /*!< Size = 192 (0xc0)                                                         */

/**
  * @brief Controller area network (CAN)
  */
typedef struct
{
  /**
   * @brief     CAN Each mailbox contains the sending mailbox identifier register
    */
  union
  {
    __IOM uint32_t TXI;

    struct
    {
      __IOM uint32_t TXRQ      : 1;
      __IOM uint32_t RTR       : 1;
      __IOM uint32_t EXIDEN    : 1;
      __IOM uint32_t EXID      : 18;
      __IOM uint32_t STID      : 11;
    } TXI_B;
  };

  /**
   * @brief     CAN Send the mailbox data length and timestamp register
    */
  union
  {
    __IOM uint32_t TXDLT;

    struct
    {
      __IOM uint32_t TXDL        : 4;
      __IM  uint32_t RESERVED1    : 4;
      __IOM uint32_t TXTS       : 1;
      __IM  uint32_t RESERVED2    : 7;
      __IOM uint32_t MTS        : 16;
    } TXDLT_B;
  };

  /**
   * @brief     CAN Send mailbox low byte data register
    */
  union
  {
    __IOM uint32_t TXDL;

    struct
    {
      __IOM uint32_t DATA1      : 8;
      __IOM uint32_t DATA2      : 8;
      __IOM uint32_t DATA3      : 8;
      __IOM uint32_t DATA4      : 8;
    } TXDL_B;
  };

  /**
   * @brief     CAN Send mailbox High byte data register
    */
  union
  {
    __IOM uint32_t TXDH;

    struct
    {
      __IOM uint32_t DATA5      : 8;
      __IOM uint32_t DATA6      : 8;
      __IOM uint32_t DATA7      : 8;
      __IOM uint32_t DATA8      : 8;
    } TXDH_B;
  };
} CAN_TxMailBox_T;

typedef struct
{
  /**
   * @brief     CAN Each mailbox contains the receive mailbox identifier register
    */
  union
  {
    __IOM uint32_t RXI;

    struct
    {
      __IM  uint32_t RESERVED1    : 1;
      __IOM uint32_t RTR         : 1;
      __IOM uint32_t EXIDEN      : 1;
      __IOM uint32_t EXID        : 18;
      __IOM uint32_t STID        : 11;
    } RXI_B;
  };

  /**
   * @brief     CAN receive the mailbox data length and timestamp register
    */
  union
  {
    __IOM uint32_t RXDLT;

    struct
    {
      __IOM uint32_t RXDL        : 4;
      __IM  uint32_t RESERVED1    : 4;
      __IOM uint32_t FMI       : 8;
      __IOM uint32_t MTS        : 16;
    } RXDLT_B;
  };

  /**
   * @brief     CAN receive mailbox low byte data register
    */
  union
  {
    __IOM uint32_t RXDL;

    struct
    {
      __IOM uint32_t DATA1      : 8;
      __IOM uint32_t DATA2      : 8;
      __IOM uint32_t DATA3      : 8;
      __IOM uint32_t DATA4      : 8;
    } RXDL_B;
  };

  /**
   * @brief     CAN receive mailbox High byte data register
    */
  union
  {
    __IOM uint32_t RXDH;

    struct
    {
      __IOM uint32_t DATA5      : 8;
      __IOM uint32_t DATA6      : 8;
      __IOM uint32_t DATA7      : 8;
      __IOM uint32_t DATA8      : 8;
    } RXDH_B;
  };
} CAN_RxMailBox_T;

typedef struct
{
  /**
  * @brief     CAN Filter1 register
  */
  union
  {
    __IOM uint32_t  F1;

    struct
    {
      __IOM uint32_t FB1     :1;
      __IOM uint32_t FB2     :1;
      __IOM uint32_t FB3     :1;
      __IOM uint32_t FB4     :1;
      __IOM uint32_t FB5     :1;
      __IOM uint32_t FB6     :1;
      __IOM uint32_t FB7     :1;
      __IOM uint32_t FB8     :1;
      __IOM uint32_t FB9     :1;
      __IOM uint32_t FB10     :1;
      __IOM uint32_t FB11     :1;
      __IOM uint32_t FB12     :1;
      __IOM uint32_t FB13     :1;
      __IOM uint32_t FB14     :1;
      __IOM uint32_t FB15     :1;
      __IOM uint32_t FB16     :1;
      __IOM uint32_t FB17     :1;
      __IOM uint32_t FB18     :1;
      __IOM uint32_t FB19     :1;
      __IOM uint32_t FB20     :1;
      __IOM uint32_t FB21     :1;
      __IOM uint32_t FB22     :1;
      __IOM uint32_t FB23     :1;
      __IOM uint32_t FB24     :1;
      __IOM uint32_t FB25     :1;
      __IOM uint32_t FB26     :1;
      __IOM uint32_t FB27     :1;
      __IOM uint32_t FB28     :1;
      __IOM uint32_t FB29     :1;
      __IOM uint32_t FB30     :1;
      __IOM uint32_t FB31     :1;
      __IOM uint32_t FB32     :1;
    } F1_B;
  };

  /**
  * @brief     CAN Filter2 register
  */
  union
  {
    __IOM uint32_t  F2;

    struct
    {
      __IOM uint32_t FB1     :1;
      __IOM uint32_t FB2     :1;
      __IOM uint32_t FB3     :1;
      __IOM uint32_t FB4     :1;
      __IOM uint32_t FB5     :1;
      __IOM uint32_t FB6     :1;
      __IOM uint32_t FB7     :1;
      __IOM uint32_t FB8     :1;
      __IOM uint32_t FB9     :1;
      __IOM uint32_t FB10     :1;
      __IOM uint32_t FB11     :1;
      __IOM uint32_t FB12     :1;
      __IOM uint32_t FB13     :1;
      __IOM uint32_t FB14     :1;
      __IOM uint32_t FB15     :1;
      __IOM uint32_t FB16     :1;
      __IOM uint32_t FB17     :1;
      __IOM uint32_t FB18     :1;
      __IOM uint32_t FB19     :1;
      __IOM uint32_t FB20     :1;
      __IOM uint32_t FB21     :1;
      __IOM uint32_t FB22     :1;
      __IOM uint32_t FB23     :1;
      __IOM uint32_t FB24     :1;
      __IOM uint32_t FB25     :1;
      __IOM uint32_t FB26     :1;
      __IOM uint32_t FB27     :1;
      __IOM uint32_t FB28     :1;
      __IOM uint32_t FB29     :1;
      __IOM uint32_t FB30     :1;
      __IOM uint32_t FB31     :1;
      __IOM uint32_t FB32     :1;
    } F2_B;
  };
} CAN_FilterRegister_T;


/**
 * @brief     CAN register
 */
typedef struct
{
  /**
   * @brief     CAN Master control register
    */
  union
  {
    __IOM uint32_t MCTRL;

    struct
    {
      __IOM uint32_t INIT       : 1;
      __IOM uint32_t SLEEP      : 1;
      __IOM uint32_t TX_PS      : 1;
      __IOM uint32_t RFLOCK     : 1;
      __IOM uint32_t ARTDIS     : 1;
      __IOM uint32_t AWUPM      : 1;
      __IOM uint32_t ABOM       : 1;
      __IOM uint32_t TTCM       : 1;
      __IM  uint32_t RESERVED1    : 7;
      __IOM uint32_t RESET      : 1;
      __IOM uint32_t DBF        : 1;
      __IM  uint32_t RESERVED2    : 15;
    } MCTRL_B;
  };

  /**
   * @brief     CAN Master States register
    */
  union
  {
    __IOM uint32_t MSTS;

    struct
    {
      __IOM uint32_t INITF       : 1;
      __IOM uint32_t SLAK        : 1;
      __IOM uint32_t ERRIF       : 1;
      __IOM uint32_t WUPIF       : 1;
      __IOM uint32_t SLPIF       : 1;
      __IM uint32_t RESERVED1   : 3;
      __IOM uint32_t TX          : 1;
      __IOM uint32_t RX          : 1;
      __IOM uint32_t LST_SAMP    : 1;
      __IOM uint32_t RX_L        : 1;
      __IM uint32_t RESERVED2  : 20;
    } MSTS_B;
  };

  /**
   * @brief     CAN Send States register
    */
  union
  {
    __IOM uint32_t TXSTS;

    struct
    {
      __IOM uint32_t EORM1     : 1;
      __IOM uint32_t TCM1      : 1;
      __IOM uint32_t ALSTM1    : 1;
      __IOM uint32_t FOTM1     : 1;
      __IM uint32_t RESERVED1     : 1;
      __IOM uint32_t ATRM1     : 1;
	  
      __IOM uint32_t EORM2     : 1;
      __IOM uint32_t TCM2      : 1;
      __IOM uint32_t ALSTM2    : 1;
      __IOM uint32_t FOTM2     : 1;
      __IM uint32_t RESERVED2     : 1;
      __IOM uint32_t ATRM2     : 1;
	  
      __IOM uint32_t EORM3     : 1;
      __IOM uint32_t TCM3      : 1;
      __IOM uint32_t ALSTM3    : 1;
      __IOM uint32_t FOTM3     : 1;
      __IM uint32_t RESERVED3  : 1;
      __IOM uint32_t ATRM3     : 1;
	  
      __IOM uint32_t EMN        : 2;
      __IOM uint32_t TXME1      : 1;
      __IOM uint32_t TXME2      : 1;
      __IOM uint32_t TXME3      : 1;
      __IOM uint32_t LOWMF1     : 1;
      __IOM uint32_t LOWMF2     : 1;
      __IOM uint32_t LOWMF3     : 1;
    } TXSTS_B;
  };

  /**
   * @brief     CAN Receive FIFO1 register
    */
  union
  {
    __IOM uint32_t RF1;

    struct
    {
      __IOM uint32_t FMNP1     : 2;
      __IM uint32_t RESERVED1 : 1;
      __IOM uint32_t FULL1     : 1;
      __IOM uint32_t FOF1      : 1;
      __IOM uint32_t RFOM1     : 1;
      __IM uint32_t RESERVED2 : 26;
    } RF1_B;
  };

  /**
   * @brief     CAN Receive FIFO2 register
    */
  union
  {
    __IOM uint32_t RF2;

    struct
    {
      __IOM uint32_t FMNP2     : 2;
      __IM uint32_t RESERVED1 : 1;
      __IOM uint32_t FULL2     : 1;
      __IOM uint32_t FOF2      : 1;
      __IOM uint32_t RFOM2     : 1;
      __IM uint32_t RESERVED2 : 26;
    } RF2_B;
  };

  /**
   * @brief     CAN Interrupts register
    */
  union
  {
    __IOM uint32_t IEN;

    struct
    {
      __IOM uint32_t EORMIEN   : 1;
      __IOM uint32_t FMNPIEN1  : 1;
      __IOM uint32_t FFIEN1    : 1;
      __IOM uint32_t FOFIEN1   : 1;
      __IOM uint32_t FMNPIEN2  : 1;
      __IOM uint32_t FFIEN2    : 1;
      __IOM uint32_t FOFIEN2   : 1;
      __IM uint32_t RESERVED1 : 1;
      __IOM uint32_t EWGIEN    : 1;
      __IOM uint32_t EPVIEN    : 1;
      __IOM uint32_t BOFIEN    : 1;
      __IOM uint32_t LECIEN    : 1;
      __IM uint32_t RESERVED2 : 3;
      __IOM uint32_t ERRIEN    : 1;
      __IOM uint32_t WUPIEN    : 1;
      __IOM uint32_t SLPIEN    : 1;
      __IM uint32_t RESERVED3 : 14;
    } IEN_B;
  };

  /**
   * @brief     CAN Error States register
    */
  union
  {
    __IOM uint32_t ESTS;

    struct
    {
      __IM uint32_t EWF      : 1;
      __IM uint32_t EPF      : 1;
      __IM uint32_t BOF      : 1;
      __IM uint32_t RESERVED1 : 1;
      __IOM uint32_t LEC     : 3;
      __IM uint32_t RESERVED2 : 9;
      __IM uint32_t TXEC      : 8;
      __IM uint32_t RXEC      : 8;
    } ESTS_B;
  };

  /**
   * @brief     CAN Bit Time register
    */
  union
  {
    __IOM uint32_t BT;

    struct
    {
      __IOM uint32_t BRD      : 10;
      __IM uint32_t RESERVED1 : 6;
      __IOM uint32_t TS1      : 4;
      __IOM uint32_t TS2      : 3;
      __IM uint32_t RESERVED2 : 1;
      __IOM uint32_t RSJW     : 2;
      __IM uint32_t RESERVED3 : 4;
      __IOM uint32_t LBM      : 1;
      __IOM uint32_t SILM     : 1;
    } BT_B;
  };

  __IM uint32_t RESERVED0[88];

  CAN_TxMailBox_T sTxMailBox[3];
  CAN_RxMailBox_T sRxMailBox[3];

  __IM uint32_t RESERVED1[12];

  /**
   * @brief     CAN Filter the master control register
    */
  union
  {
    __IOM uint32_t FMCTRL;

    struct
    {
      __IOM uint32_t FINIT    : 1;
      __IM uint32_t RESERVED : 31;
    } FMCTRL_B;
  };

  /**
   * @brief     CAN Filter register
    */
  union
  {
    __IOM uint32_t FM;

    struct
    {
      __IOM uint32_t FBM1     :1;
      __IOM uint32_t FBM2     :1;
      __IOM uint32_t FBM3     :1;
      __IOM uint32_t FBM4     :1;
      __IOM uint32_t FBM5     :1;
      __IOM uint32_t FBM6     :1;
      __IOM uint32_t FBM7     :1;
      __IOM uint32_t FBM8     :1;
      __IOM uint32_t FBM9     :1;
      __IOM uint32_t FBM10     :1;
      __IOM uint32_t FBM11     :1;
      __IOM uint32_t FBM12     :1;
      __IOM uint32_t FBM13     :1;
      __IOM uint32_t FBM14     :1;
      __IOM uint32_t FBM15     :1;
      __IOM uint32_t FBM16     :1;
      __IOM uint32_t FBM17     :1;
      __IOM uint32_t FBM18     :1;
      __IOM uint32_t FBM19     :1;
      __IOM uint32_t FBM20     :1;
      __IOM uint32_t FBM21     :1;
      __IOM uint32_t FBM22     :1;
      __IOM uint32_t FBM23     :1;
      __IOM uint32_t FBM24     :1;
      __IOM uint32_t FBM25     :1;
      __IOM uint32_t FBM26     :1;
      __IOM uint32_t FBM27     :1;
      __IOM uint32_t FBM28     :1;
      __IM uint32_t RESERVED : 4;
    } FM_B;
  };

  __IM uint32_t RESERVED2;


  /**
   * @brief     CAN Filter bit width register
    */
  union
  {
    __IOM uint32_t FBW;

    struct
    {
      __IOM uint32_t BW1     :1;
      __IOM uint32_t BW2     :1;
      __IOM uint32_t BW3     :1;
      __IOM uint32_t BW4     :1;
      __IOM uint32_t BW5     :1;
      __IOM uint32_t BW6     :1;
      __IOM uint32_t BW7     :1;
      __IOM uint32_t BW8     :1;
      __IOM uint32_t BW9     :1;
      __IOM uint32_t BW10     :1;
      __IOM uint32_t BW11     :1;
      __IOM uint32_t BW12     :1;
      __IOM uint32_t BW13     :1;
      __IOM uint32_t BW14     :1;
      __IOM uint32_t BW15     :1;
      __IOM uint32_t BW16     :1;
      __IOM uint32_t BW17     :1;
      __IOM uint32_t BW18     :1;
      __IOM uint32_t BW19     :1;
      __IOM uint32_t BW20     :1;
      __IOM uint32_t BW21     :1;
      __IOM uint32_t BW22     :1;
      __IOM uint32_t BW23     :1;
      __IOM uint32_t BW24     :1;
      __IOM uint32_t BW25     :1;
      __IOM uint32_t BW26     :1;
      __IOM uint32_t BW27     :1;
      __IOM uint32_t BW28     :1;
      __IM uint32_t RESERVED : 4;
    } FBW_B;
  };

  __IM uint32_t RESERVED3;

  /**
   * @brief     CAN Filter FIFO associated registers
    */
  union
  {
    __IOM uint32_t FFA;

    struct
    {
      __IOM uint32_t FFA1     :1;
      __IOM uint32_t FFA2     :1;
      __IOM uint32_t FFA3     :1;
      __IOM uint32_t FFA4     :1;
      __IOM uint32_t FFA5     :1;
      __IOM uint32_t FFA6     :1;
      __IOM uint32_t FFA7     :1;
      __IOM uint32_t FFA8     :1;
      __IOM uint32_t FFA9     :1;
      __IOM uint32_t FFA10     :1;
      __IOM uint32_t FFA11     :1;
      __IOM uint32_t FFA12     :1;
      __IOM uint32_t FFA13     :1;
      __IOM uint32_t FFA14     :1;
      __IOM uint32_t FFA15     :1;
      __IOM uint32_t FFA16     :1;
      __IOM uint32_t FFA17     :1;
      __IOM uint32_t FFA18     :1;
      __IOM uint32_t FFA19     :1;
      __IOM uint32_t FFA20     :1;
      __IOM uint32_t FFA21     :1;
      __IOM uint32_t FFA22     :1;
      __IOM uint32_t FFA23     :1;
      __IOM uint32_t FFA24     :1;
      __IOM uint32_t FFA25     :1;
      __IOM uint32_t FFA26     :1;
      __IOM uint32_t FFA27     :1;
      __IOM uint32_t FFA28     :1;
      __IM uint32_t RESERVED : 4;
    } FFA_B;
  };

  __IM uint32_t RESERVED4;
  /**
   * @brief     CAN Filter activation register
    */
  union
  {
    __IOM uint32_t FEN;

    struct
    {
      __IOM uint32_t FEN1     :1;
      __IOM uint32_t FEN2     :1;
      __IOM uint32_t FEN3     :1;
      __IOM uint32_t FEN4     :1;
      __IOM uint32_t FEN5     :1;
      __IOM uint32_t FEN6     :1;
      __IOM uint32_t FEN7     :1;
      __IOM uint32_t FEN8     :1;
      __IOM uint32_t FEN9     :1;
      __IOM uint32_t FEN10     :1;
      __IOM uint32_t FEN11     :1;
      __IOM uint32_t FEN12     :1;
      __IOM uint32_t FEN13     :1;
      __IOM uint32_t FEN14     :1;
      __IOM uint32_t FEN15     :1;
      __IOM uint32_t FEN16     :1;
      __IOM uint32_t FEN17     :1;
      __IOM uint32_t FEN18     :1;
      __IOM uint32_t FEN19     :1;
      __IOM uint32_t FEN20     :1;
      __IOM uint32_t FEN21     :1;
      __IOM uint32_t FEN22     :1;
      __IOM uint32_t FEN23     :1;
      __IOM uint32_t FEN24     :1;
      __IOM uint32_t FEN25     :1;
      __IOM uint32_t FEN26     :1;
      __IOM uint32_t FEN27     :1;
      __IOM uint32_t FEN28     :1;
      __IM uint32_t RESERVED : 4;
    } FEN_B;
  };

  __IM uint32_t RESERVED5[8];

  CAN_FilterRegister_T sFilterRegister[14];

} CAN_T;

/**
  * @brief Inter integrated circuit 1 (I2C)
  */

typedef struct {                                /*!< (@ 0x40005400) I2C Structure                                             */
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000000) Control register 1                                         */
    
    struct {
      __IOM uint32_t I2CEN      : 1;            /*!< [0..0] Peripheral enable                                                  */
      __IOM uint32_t SMB        : 1;            /*!< [1..1] SMBus mode                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t SMBT       : 1;            /*!< [3..3] SMBus type                                                         */
      __IOM uint32_t ARPEN      : 1;            /*!< [4..4] ARP enable                                                         */
      __IOM uint32_t PECEN      : 1;            /*!< [5..5] PEC enable                                                         */
      __IOM uint32_t BCEN       : 1;            /*!< [6..6] General call enable                                                */
      __IOM uint32_t STRDIS     : 1;            /*!< [7..7] Clock stretching disable (Slave mode)                              */
      __IOM uint32_t STA        : 1;            /*!< [8..8] Start generation                                                   */
      __IOM uint32_t STOP       : 1;            /*!< [9..9] Stop generation                                                    */
      __IOM uint32_t ACKEN      : 1;            /*!< [10..10] Acknowledge enable                                               */
      __IOM uint32_t ACKPOS     : 1;            /*!< [11..11] Acknowledge/PEC Position (for data reception)                    */
      __IOM uint32_t TPECEN     : 1;            /*!< [12..12] Packet error checking                                            */
      __IOM uint32_t SMB_ALT    : 1;            /*!< [13..13] SMBus alert                                                      */
      __IM  uint32_t            : 1;
      __IOM uint32_t SWRST      : 1;            /*!< [15..15] Software reset                                                   */
    } CTRL1_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000004) Control register 2                                         */
    
    struct {
      __IOM uint32_t FREQ       : 6;            /*!< [5..0] Peripheral clock frequency                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t ERRIE      : 1;            /*!< [8..8] Error interrupt enable                                             */
      __IOM uint32_t EVTIE      : 1;            /*!< [9..9] Event interrupt enable                                             */
      __IOM uint32_t BUFIE      : 1;            /*!< [10..10] Buffer interrupt enable                                          */
      __IOM uint32_t DMAEN      : 1;            /*!< [11..11] DMA requests enable                                              */
      __IOM uint32_t LAST       : 1;            /*!< [12..12] DMA last transfer                                                */
    } CTRL2_B;
  } ;
  
  union {
    __IOM uint32_t ADD1;                        /*!< (@ 0x00000008) Own address register 1                                     */
    
    struct {
      __IOM uint32_t ADD0       : 1;            /*!< [0..0] Interface address                                                  */
      __IOM uint32_t ADD1_7     : 7;            /*!< [7..1] Interface address                                                  */
      __IOM uint32_t ADD8_9     : 2;            /*!< [9..8] Interface address                                                  */
      __IM  uint32_t            : 5;
      __IOM uint32_t ADDCFG     : 1;            /*!< [15..15] ADDCFG                                                           */
      __IOM uint32_t ADDMODE    : 1;            /*!< [16..16] Addressing mode (slave mode)                                     */
    } ADD1_B;
  } ;
  
  union {
    __IOM uint32_t ADD2;                        /*!< (@ 0x0000000C) Own address register 2                                     */
    
    struct {
      __IOM uint32_t DUALEN     : 1;            /*!< [0..0] Dual addressing mode enable                                        */
      __IOM uint32_t ADD2       : 7;            /*!< [7..1] Interface address                                                  */
    } ADD2_B;
  } ;
  
  union {
    __IOM uint32_t DATA;                        /*!< (@ 0x00000010) Data register                                              */
    
    struct {
      __IOM uint32_t DATA       : 8;            /*!< [7..0] 8-bit data register                                                */
    } DATA_B;
  } ;
  
  union {
    __IOM uint32_t STS1;                        /*!< (@ 0x00000014) Status register 1                                          */
    
    struct {
      __IM  uint32_t SBTCF      : 1;            /*!< [0..0] Start bit (Master mode)                                            */
      __IM  uint32_t ADDRF      : 1;            /*!< [1..1] Address sent (master mode)/matched (slave mode)                    */
      __IM  uint32_t BTCF       : 1;            /*!< [2..2] Byte transfer finished                                             */
      __IM  uint32_t ADDR10F    : 1;            /*!< [3..3] 10-bit header sent (Master mode)                                   */
      __IM  uint32_t SBDF       : 1;            /*!< [4..4] Stop detection (slave mode)                                        */
      __IM  uint32_t            : 1;
      __IM  uint32_t RXBENF     : 1;            /*!< [6..6] Data register not empty (receivers)                                */
      __IM  uint32_t TXBENF     : 1;            /*!< [7..7] Data register empty (transmitters)                                 */
      __IOM uint32_t BEF        : 1;            /*!< [8..8] Bus error                                                          */
      __IOM uint32_t ALF        : 1;            /*!< [9..9] Arbitration lost (master mode)                                     */
      __IOM uint32_t AEF        : 1;            /*!< [10..10] Acknowledge failure                                              */
      __IOM uint32_t OUF        : 1;            /*!< [11..11] Overrun/Underrun                                                 */
      __IOM uint32_t PECEF      : 1;            /*!< [12..12] PEC Error in reception                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t TIMEOUT    : 1;            /*!< [14..14] Timeout or Tlow error                                            */
      __IOM uint32_t SMB_ALTF   : 1;            /*!< [15..15] SMBus alert                                                      */
    } STS1_B;
  } ;
  
  union {
    __IM  uint32_t STS2;                        /*!< (@ 0x00000018) Status register 2                                          */
    
    struct {
      __IM  uint32_t MMF        : 1;            /*!< [0..0] Master/slave                                                       */
      __IM  uint32_t BUSYF      : 1;            /*!< [1..1] Bus busy                                                           */
      __IM  uint32_t RWMF       : 1;            /*!< [2..2] Transmitter/receiver                                               */
      __IM  uint32_t            : 1;
      __IM  uint32_t RBF        : 1;            /*!< [4..4] General call address (Slave mode)                                  */
      __IM  uint32_t SMB_DAF    : 1;            /*!< [5..5] SMBus device default address (Slave mode)                          */
      __IM  uint32_t SMB_HHF    : 1;            /*!< [6..6] SMBus host header (Slave mode)                                     */
      __IM  uint32_t DMAF       : 1;            /*!< [7..7] Dual flag (Slave mode)                                             */
      __IM  uint32_t PEC_DATA   : 8;            /*!< [15..8] acket error checking register                                     */
    } STS2_B;
  } ;
  
  union {
    __IOM uint32_t CLKCTRL;                     /*!< (@ 0x0000001C) Clock control register                                     */
    
    struct {
      __IOM uint32_t CDR        : 12;           /*!< [11..0] Clock control register in Fast/Standard mode (Master
                                                     mode)                                                                     */
      __IM  uint32_t            : 2;
      __IOM uint32_t FMDC       : 1;            /*!< [14..14] Fast mode duty cycle                                             */
      __IOM uint32_t FASTMODE   : 1;            /*!< [15..15] I2C master mode selection                                        */
    } CLKCTRL_B;
  } ;
  
  union {
    __IOM uint32_t TRISE;                       /*!< (@ 0x00000020) TRISE register                                             */
    
    struct {
      __IOM uint32_t TRISE      : 6;            /*!< [5..0] Maximum rise time in Fast/Standard mode (Master mode)              */
    } TRISE_B;
  } ;
  __IM  uint32_t  RESERVED[55];
  
  union {
    __IOM uint32_t SWITCH;                      /*!< (@ 0x00000100) I2C Switching register                                     */
    
    struct {
      __IOM uint32_t SWITCH     : 1;            /*!< [0..0] I2C Switching                                                      */
    } SWITCH_B;
  } ;
} I2C_T;                                    /*!< Size = 260 (0x104)                                                        */


typedef struct
{
    __IO uint16_t RDP;
    __IO uint16_t USER;
    __IO uint16_t Data0;
    __IO uint16_t Data1;
    __IO uint16_t WRP0;
    __IO uint16_t WRP1;
    __IO uint16_t WRP2;
    __IO uint16_t WRP3;
} OB_T;

/** 
  * @brief Analog to Digital Converter
  */

typedef struct {                                /*!< (@ 0x40003000) IWDT Structure                                             */
  
  union {
    __OM  uint32_t KEYWORD;                     /*!< (@ 0x00000000) Key register (IWDT_KEYWORD)                                */
    
    struct {
      __OM  uint32_t KEYWORD    : 16;           /*!< [15..0] Key value                                                         */
    } KEYWORD_B;
  } ;
  
  union {
    __IOM uint32_t DIV;                         /*!< (@ 0x00000004) Frequency Divider register (IWDT_DIV)                      */
    
    struct {
      __IOM uint32_t DIV        : 3;            /*!< [2..0] Prescaler divider                                                  */
    } DIV_B;
  } ;
  
  union {
    __IOM uint32_t CNTRLD;                      /*!< (@ 0x00000008) Reload values register (IWDT_CNTRLD)                       */
    
    struct {
      __IOM uint32_t CNTRLD     : 12;           /*!< [11..0] Watchdog counter reload value                                     */
    } CNTRLD_B;
  } ;
  
  union {
    __IM  uint32_t STS;                         /*!< (@ 0x0000000C) Status register (IWDT_STS)                                 */
    
    struct {
      __IM  uint32_t DVU        : 1;            /*!< [0..0] Watchdog prescaler value update                                    */
      __IM  uint32_t CNTRU      : 1;            /*!< [1..1] Watchdog counter reload value update                               */
    } STS_B;
  } ;
} IWDT_T;                                    /*!< Size = 16 (0x10)                                                          */

/**
  * @brief Window watchdog (WWDT)
  */

typedef struct {                                /*!< (@ 0x40002C00) WWDT Structure                                             */
  
  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control register (WWDT_CR)                                 */
    
    struct {
      __IOM uint32_t CNT        : 7;            /*!< [6..0] 7-bit counter (MSB to LSB)                                         */
      __IOM uint32_t WWDTEN     : 1;            /*!< [7..7] Activation bit                                                     */
    } CTRL_B;
  } ;
  
  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000004) Configuration register (WWDT_CFR)                          */
    
    struct {
      __IOM uint32_t WDDATA     : 7;            /*!< [6..0] 7-bit window value                                                 */
      __IOM uint32_t WDTTB      : 2;            /*!< [8..7] Timer Base                                                         */
      __IOM uint32_t EWIEN      : 1;            /*!< [9..9] Early Wakeup Interrupt                                             */
    } CFG_B;
  } ;
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x00000008) Status register (WWDT_SR)                                  */
    
    struct {
      __IOM uint32_t EWIF       : 1;            /*!< [0..0] Early Wakeup Interrupt                                             */
    } STS_B;
  } ;
} WWDT_T;                                    /*!< Size = 12 (0xc)                                                           */

/**
  * @brief Real time clock (RTC)
  */

typedef struct {                                /*!< (@ 0x40002800) RTC Structure                                              */
  
  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t SECIEN     : 1;            /*!< [0..0] Second interrupt Enable                                            */
      __IOM uint32_t ALMIEN     : 1;            /*!< [1..1] Alarm interrupt Enable                                             */
      __IOM uint32_t OWIEN      : 1;            /*!< [2..2] Overflow interrupt Enable                                          */
    } CTRL_B;
  } ;
  
  union {
    __IOM uint32_t CSTS;                        /*!< (@ 0x00000004) Control and State register                                 */
    
    struct {
      __IOM uint32_t SECIF      : 1;            /*!< [0..0] Second Flag                                                        */
      __IOM uint32_t ALMIF      : 1;            /*!< [1..1] Alarm Flag                                                         */
      __IOM uint32_t OWIF       : 1;            /*!< [2..2] Overflow Flag                                                      */
      __IOM uint32_t SYNCF      : 1;            /*!< [3..3] Registers Synchronized Flag                                        */
      __IOM uint32_t CFGEN      : 1;            /*!< [4..4] Configuration Flag                                                 */
      __IM  uint32_t RTOPC      : 1;            /*!< [5..5] RTC operation OFF                                                  */
    } CSTS_B;
  } ;
  
  union {
    __OM  uint32_t RDIVH;                       /*!< (@ 0x00000008) RTC predivision loading register High Bit                  */
    
    struct {
      __OM  uint32_t DIV        : 4;            /*!< [3..0] RTC Prescaler Load Register High                                   */
    } RDIVH_B;
  } ;
  
  union {
    __OM  uint32_t RDIVL;                       /*!< (@ 0x0000000C) RTC predivision loading register Low Bit                   */
    
    struct {
      __OM  uint32_t DIV        : 16;           /*!< [15..0] RTC Prescaler Divider Register Low                                */
    } RDIVL_B;
  } ;
  
  union {
    __IM  uint32_t DIVH;                        /*!< (@ 0x00000010) RTC predivider remainder register High Bit                 */
    
    struct {
      __IM  uint32_t DIV        : 4;            /*!< [3..0] RTC prescaler divider register high                                */
    } DIVH_B;
  } ;
  
  union {
    __IM  uint32_t DIVL;                        /*!< (@ 0x00000014) RTC predivider remainder register Low Bit                  */
    
    struct {
      __IM  uint32_t DIV        : 16;           /*!< [15..0] RTC prescaler divider register Low                                */
    } DIVL_B;
  } ;
  
  union {
    __IOM uint32_t CNTH;                        /*!< (@ 0x00000018) RTC count register High Bit                                */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] RTC counter register high                                         */
    } CNTH_B;
  } ;
  
  union {
    __IOM uint32_t CNTL;                        /*!< (@ 0x0000001C) RTC count register Low Bit                                 */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] RTC counter register Low                                          */
    } CNTL_B;
  } ;
  
  union {
    __OM  uint32_t ALMH;                        /*!< (@ 0x00000020) RTC alarm clock register High Bit                          */
    
    struct {
      __OM  uint32_t ALM        : 16;           /*!< [15..0] RTC alarm register high                                           */
    } ALMH_B;
  } ;
  
  union {
    __OM  uint32_t ALML;                        /*!< (@ 0x00000024) RTC alarm clock register Low Bit                           */
    
    struct {
      __OM  uint32_t ALM        : 16;           /*!< [15..0] RTC alarm register low                                            */
    } ALML_B;
  } ;
} RTC_T;                                     /*!< Size = 40 (0x28)                                                          */

/**
  * @brief General purpose timer (TMR2)
  */

typedef struct {                                /*!< (@ 0x40000000) TMR2 Structure                                             */
  
  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000000) control register 1                                         */
    
    struct {
      __IOM uint32_t CNTEN      : 1;            /*!< [0..0] Counter enable                                                     */
      __IOM uint32_t NGUE       : 1;            /*!< [1..1] Update disable                                                     */
      __IOM uint32_t UES        : 1;            /*!< [2..2] Update request source                                              */
      __IOM uint32_t SPMEN      : 1;            /*!< [3..3] One-pulse mode                                                     */
      __IOM uint32_t CNTDIR     : 1;            /*!< [4..4] Direction                                                          */
      __IOM uint32_t CNTMODE    : 2;            /*!< [6..5] Center-aligned mode selection                                      */
      __IOM uint32_t ARBEN      : 1;            /*!< [7..7] Auto-reload preload enable                                         */
      __IOM uint32_t CKDR       : 2;            /*!< [9..8] Clock division                                                     */
    } CTRL1_B;
  } ;
  
  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000004) control register 2                                         */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t MMFC       : 3;            /*!< [6..4] Master mode selection                                              */
      __IOM uint32_t TI1IS      : 1;            /*!< [7..7] TI1 selection                                                      */
    } CTRL2_B;
  } ;
  
  union {
    __IOM uint32_t SMCTRL;                      /*!< (@ 0x00000008) slave mode control register                                */
    
    struct {
      __IOM uint32_t SMFC       : 3;            /*!< [2..0] Slave mode selection                                               */
      __IM  uint32_t            : 1;
      __IOM uint32_t ITC        : 3;            /*!< [6..4] Trigger selection                                                  */
      __IOM uint32_t MSMEN      : 1;            /*!< [7..7] Master/Slave mode                                                  */
      __IOM uint32_t ETFC       : 4;            /*!< [11..8] External trigger filter                                           */
      __IOM uint32_t ETDC       : 2;            /*!< [13..12] External trigger prescaler                                       */
      __IOM uint32_t ECM2EN     : 1;            /*!< [14..14] External clock enable                                            */
      __IOM uint32_t ETPC       : 1;            /*!< [15..15] External trigger polarity                                        */
    } SMCTRL_B;
  } ;
  
  union {
    __IOM uint32_t DIEN;                        /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
    
    struct {
      __IOM uint32_t UDIEN      : 1;            /*!< [0..0] Update interrupt enable                                            */
      __IOM uint32_t CH1CCIEN   : 1;            /*!< [1..1] Capture/Compare 1 interrupt enable                                 */
      __IOM uint32_t CH2CCIEN   : 1;            /*!< [2..2] Capture/Compare 2 interrupt enable                                 */
      __IOM uint32_t CH3CCIEN   : 1;            /*!< [3..3] Capture/Compare 3 interrupt enable                                 */
      __IOM uint32_t CH4CCIEN   : 1;            /*!< [4..4] Capture/Compare 4 interrupt enable                                 */
      __IM  uint32_t            : 1;
      __IOM uint32_t TRGIEN     : 1;            /*!< [6..6] Trigger interrupt enable                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t UDEN       : 1;            /*!< [8..8] Update DMA request enable                                          */
      __IOM uint32_t CH1CCDEN   : 1;            /*!< [9..9] Capture/Compare 1 DMA request enable                               */
      __IOM uint32_t CH2CCDEN   : 1;            /*!< [10..10] Capture/Compare 2 DMA request enable                             */
      __IOM uint32_t CH3CCDEN   : 1;            /*!< [11..11] Capture/Compare 3 DMA request enable                             */
      __IOM uint32_t CH4CCDEN   : 1;            /*!< [12..12] Capture/Compare 4 DMA request enable                             */
      __IM  uint32_t            : 1;
      __IOM uint32_t TDEN       : 1;            /*!< [14..14] Trigger DMA request enable                                       */
    } DIEN_B;
  } ;
  
  union {
    __IOM uint32_t STS;                         /*!< (@ 0x00000010) status register                                            */
    
    struct {
      __IOM uint32_t UDIF       : 1;            /*!< [0..0] Update interrupt flag                                              */
      __IOM uint32_t CH1CCIF    : 1;            /*!< [1..1] Capture/compare 1 interrupt flag                                   */
      __IOM uint32_t CH2CCIF    : 1;            /*!< [2..2] Capture/Compare 2 interrupt flag                                   */
      __IOM uint32_t CH3CCIF    : 1;            /*!< [3..3] Capture/Compare 3 interrupt flag                                   */
      __IOM uint32_t CH4CCIF    : 1;            /*!< [4..4] Capture/Compare 4 interrupt flag                                   */
      __IM  uint32_t            : 1;
      __IOM uint32_t TRGIF      : 1;            /*!< [6..6] Trigger interrupt flag                                             */
      __IM  uint32_t            : 2;
      __IOM uint32_t CH1RCF     : 1;            /*!< [9..9] Capture/Compare 1 overcapture flag                                 */
      __IOM uint32_t CH2RCF     : 1;            /*!< [10..10] Capture/compare 2 overcapture flag                               */
      __IOM uint32_t CH3RCF     : 1;            /*!< [11..11] Capture/Compare 3 overcapture flag                               */
      __IOM uint32_t CH4RCF     : 1;            /*!< [12..12] Capture/Compare 4 overcapture flag                               */
    } STS_B;
  } ;
  
  union {
    __OM  uint32_t SCEG;                        /*!< (@ 0x00000014) event generation register                                  */
    
    struct {
      __OM  uint32_t UEG        : 1;            /*!< [0..0] Update generation                                                  */
      __OM  uint32_t CH1CCG     : 1;            /*!< [1..1] Capture/compare 1 generation                                       */
      __OM  uint32_t CH2CCG     : 1;            /*!< [2..2] Capture/compare 2 generation                                       */
      __OM  uint32_t CH3CCG     : 1;            /*!< [3..3] Capture/compare 3 generation                                       */
      __OM  uint32_t CH4CCG     : 1;            /*!< [4..4] Capture/compare 4 generation                                       */
      __OM  uint32_t CCUEG      : 1;            /*!< [5..5] Capture/Compare control update generation                          */
      __OM  uint32_t TEG        : 1;            /*!< [6..6] Trigger generation                                                 */
    } SCEG_B;
  } ;
  
  union {
    union {
      __IOM uint32_t CCM1_Output;               /*!< (@ 0x00000018) capture/compare mode register (output mode)                */
      
      struct {
        __IOM uint32_t CC1MS    : 2;            /*!< [1..0] Capture/Compare 1 selection                                        */
        __IOM uint32_t OC1FEN   : 1;            /*!< [2..2] Output Compare 1 fast enable                                       */
        __IOM uint32_t OC1BEN   : 1;            /*!< [3..3] Output Compare 1 preload enable                                    */
        __IOM uint32_t OC1MS    : 3;            /*!< [6..4] Output Compare 1 mode                                              */
        __IOM uint32_t OC1CEN   : 1;            /*!< [7..7] Output Compare 1 clear enable                                      */
        __IOM uint32_t CC2MS    : 2;            /*!< [9..8] Capture/Compare 2 selection                                        */
        __IOM uint32_t OC2FEN   : 1;            /*!< [10..10] Output Compare 2 fast enable                                     */
        __IOM uint32_t OC2BEN   : 1;            /*!< [11..11] Output Compare 2 preload enable                                  */
        __IOM uint32_t OC2MS    : 3;            /*!< [14..12] Output Compare 2 mode                                            */
        __IOM uint32_t OC2CEN   : 1;            /*!< [15..15] Output Compare 2 clear enable                                    */
      } CCM1_Output_B;
    } ;
    
    union {
      __IOM uint32_t CCM1_Input;                /*!< (@ 0x00000018) capture/compare mode register 1 (input mode)               */
      
      struct {
        __IOM uint32_t CC1MS    : 2;            /*!< [1..0] Capture/Compare 1 selection                                        */
        __IOM uint32_t IC1D     : 2;            /*!< [3..2] Input capture 1 prescaler                                          */
        __IOM uint32_t IC1FC    : 4;            /*!< [7..4] Input capture 1 filter                                             */
        __IOM uint32_t CC2MS    : 2;            /*!< [9..8] Capture/Compare 2 selection                                        */
        __IOM uint32_t IC2D     : 2;            /*!< [11..10] Input capture 2 prescaler                                        */
        __IOM uint32_t IC2FC    : 4;            /*!< [15..12] Input capture 2 filter                                           */
      } CCM1_Input_B;
    } ;
  };
  
  union {
    union {
      __IOM uint32_t CCM2_Output;               /*!< (@ 0x0000001C) capture/compare mode register (output mode)                */
      
      struct {
        __IOM uint32_t CC3MS    : 2;            /*!< [1..0] Capture/Compare 3 selection                                        */
        __IOM uint32_t OC3FEN   : 1;            /*!< [2..2] Output compare 3 fast enable                                       */
        __IOM uint32_t OC3BEN   : 1;            /*!< [3..3] Output compare 3 preload enable                                    */
        __IOM uint32_t OC3MS    : 3;            /*!< [6..4] Output compare 3 mode                                              */
        __IOM uint32_t OC3CEN   : 1;            /*!< [7..7] Output compare 3 clear enable                                      */
        __IOM uint32_t CC4MS    : 2;            /*!< [9..8] Capture/Compare 4 selection                                        */
        __IOM uint32_t OC4FEN   : 1;            /*!< [10..10] Output compare 4 fast enable                                     */
        __IOM uint32_t OC4BEN   : 1;            /*!< [11..11] Output compare 4 preload enable                                  */
        __IOM uint32_t OC4MS    : 3;            /*!< [14..12] Output compare 4 mode                                            */
        __IOM uint32_t OC4CEN   : 1;            /*!< [15..15] Output compare 4 clear enable                                    */
      } CCM2_Output_B;
    } ;
    
    union {
      __IOM uint32_t CCM2_Input;                /*!< (@ 0x0000001C) capture/compare mode register 2 (input mode)               */
      
      struct {
        __IOM uint32_t CC3MS    : 2;            /*!< [1..0] Capture/compare 3 selection                                        */
        __IOM uint32_t IC3D     : 2;            /*!< [3..2] Input capture 3 prescaler                                          */
        __IOM uint32_t IC3FC    : 4;            /*!< [7..4] Input capture 3 filter                                             */
        __IOM uint32_t CC4MS    : 2;            /*!< [9..8] Capture/Compare 4 selection                                        */
        __IOM uint32_t IC4D     : 2;            /*!< [11..10] Input capture 4 prescaler                                        */
        __IOM uint32_t IC4FC    : 4;            /*!< [15..12] Input capture 4 filter                                           */
      } CCM2_Input_B;
    } ;
  };
  
  union {
    __IOM uint32_t CHCTRL;                      /*!< (@ 0x00000020) capture/compare enable register                            */
    
    struct {
      __IOM uint32_t CH1CCEN    : 1;            /*!< [0..0] Capture/Compare 1 output enable                                    */
      __IOM uint32_t CH1CCP     : 1;            /*!< [1..1] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CH1OCNEN   : 1;            /*!< [2..2] Capture/Compare 1 complementary output enable                      */
      __IOM uint32_t CH1OCNP    : 1;            /*!< [3..3] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CH2CCEN    : 1;            /*!< [4..4] Capture/Compare 2 output enable                                    */
      __IOM uint32_t CH2CCP     : 1;            /*!< [5..5] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CH2OCNEN   : 1;            /*!< [6..6] Capture/Compare 2 complementary output enable                      */
      __IOM uint32_t CH2OCNP    : 1;            /*!< [7..7] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CH3CCEN    : 1;            /*!< [8..8] Capture/Compare 3 output enable                                    */
      __IOM uint32_t CH3CCP     : 1;            /*!< [9..9] Capture/Compare 3 output Polarity                                  */
      __IOM uint32_t CH3OCNEN   : 1;            /*!< [10..10] Capture/Compare 3 complementary output enable                    */
      __IOM uint32_t CH3OCNP    : 1;            /*!< [11..11] Capture/Compare 3 output Polarity                                */
      __IOM uint32_t CH4CCEN    : 1;            /*!< [12..12] Capture/Compare 4 output enable                                  */
      __IOM uint32_t CH4CCP     : 1;            /*!< [13..13] Capture/Compare 3 output Polarity                                */
    } CHCTRL_B;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] counter value                                                     */
    } CNT_B;
  } ;
  
  union {
    __IOM uint32_t DIV;                         /*!< (@ 0x00000028) prescaler                                                  */
    
    struct {
      __IOM uint32_t DIV        : 16;           /*!< [15..0] Prescaler value                                                   */
    } DIV_B;
  } ;
  
  union {
    __IOM uint32_t AOUTORLD;                    /*!< (@ 0x0000002C) auto-reload register                                       */
    
    struct {
      __IOM uint32_t AOUTORLD   : 16;           /*!< [15..0] Auto-reload value                                                 */
    } AOUTORLD_B;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t CH1CC;                       /*!< (@ 0x00000034) capture/compare register 1                                 */
    
    struct {
      __IOM uint32_t CH1CC      : 16;           /*!< [15..0] Capture/Compare 1 value                                           */
    } CH1CC_B;
  } ;
  
  union {
    __IOM uint32_t CH2CC;                       /*!< (@ 0x00000038) capture/compare register 2                                 */
    
    struct {
      __IOM uint32_t CH2CC      : 16;           /*!< [15..0] Capture/Compare 2 value                                           */
    } CH2CC_B;
  } ;
  
  union {
    __IOM uint32_t CH3CC;                       /*!< (@ 0x0000003C) capture/compare register 3                                 */
    
    struct {
      __IOM uint32_t CH3CC      : 16;           /*!< [15..0] Capture/Compare 3 value                                           */
    } CH3CC_B;
  } ;
  
  union {
    __IOM uint32_t CH4CC;                       /*!< (@ 0x00000040) capture/compare register 4                                 */
    
    struct {
      __IOM uint32_t CH4CC      : 16;           /*!< [15..0] Capture/Compare 4 value                                           */
    } CH4CC_B;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t DCTRL;                       /*!< (@ 0x00000048) DMA control register                                       */
    
    struct {
      __IOM uint32_t DBA        : 5;            /*!< [4..0] DMA base address                                                   */
      __IM  uint32_t            : 3;
      __IOM uint32_t DBL        : 5;            /*!< [12..8] DMA burst length                                                  */
    } DCTRL_B;
  } ;
  
  union {
    __IOM uint32_t DMAB;                        /*!< (@ 0x0000004C) Consecutive DMA addresses                                  */
    
    struct {
      __IOM uint32_t DMAB       : 16;           /*!< [15..0] DMA register for burst accesses                                   */
    } DMAB_B;
  } ;
} TMR2_T;                                    /*!< Size = 80 (0x50)                                                          */

/**
  * @brief Debug support (DBG)
  */

typedef struct {                                /*!< (@ 0xE0042000) DBG Structure                                              */
  
  union {
    __IM  uint32_t IDCODE;                      /*!< (@ 0x00000000) DBGMCU_IDCODE                                              */
    
    struct {
      __IM  uint32_t DEV_ID     : 12;           /*!< [11..0] DEV_ID                                                            */
      __IM  uint32_t            : 4;
      __IM  uint32_t REV_ID     : 16;           /*!< [31..16] REV_ID                                                           */
    } IDCODE_B;
  } ;
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000004) DBGMCU_CR                                                  */
    
    struct {
      __IOM uint32_t DBG_SLEEP  : 1;            /*!< [0..0] DBG_SLEEP                                                          */
      __IOM uint32_t DBG_STOP   : 1;            /*!< [1..1] DBG_STOP                                                           */
      __IOM uint32_t DBG_STANDBY : 1;           /*!< [2..2] DBG_STANDBY                                                        */
      __IM  uint32_t            : 2;
      __IOM uint32_t TRACE_IOEN : 1;            /*!< [5..5] TRACE_IOEN                                                         */
      __IOM uint32_t TRACE_MODE : 2;            /*!< [7..6] TRACE_MODE                                                         */
      __IOM uint32_t DBG_IWDT_STOP : 1;         /*!< [8..8] DBG_IWDT_STOP                                                      */
      __IOM uint32_t DBG_WWDT_STOP : 1;         /*!< [9..9] DBG_WWDT_STOP                                                      */
      __IOM uint32_t DBG_TMR1_STOP : 1;         /*!< [10..10] DBG_TMR1_STOP                                                    */
      __IOM uint32_t DBG_TMR2_STOP : 1;         /*!< [11..11] DBG_TMR2_STOP                                                    */
      __IOM uint32_t DBG_TMR3_STOP : 1;         /*!< [12..12] DBG_TMR3_STOP                                                    */
      __IOM uint32_t DBG_TMR4_STOP : 1;         /*!< [13..13] DBG_TMR4_STOP                                                    */
      __IOM uint32_t DBG_CAN1_STOP : 1;         /*!< [14..14] DBG_CAN1_STOP                                                    */
      __IOM uint32_t DBG_I2C1_SMBUS_TIMEOUT : 1;/*!< [15..15] DBG_I2C1_SMBUS_TIMEOUT                                           */
      __IOM uint32_t DBG_I2C2_SMBUS_TIMEOUT : 1;/*!< [16..16] DBG_I2C2_SMBUS_TIMEOUT                                           */
      __IOM uint32_t DBG_TMR8_STOP : 1;         /*!< [17..17] DBG_TMR8_STOP                                                    */
      __IOM uint32_t DBG_TMR5_STOP : 1;         /*!< [18..18] DBG_TMR5_STOP                                                    */
      __IOM uint32_t DBG_TMR6_STOP : 1;         /*!< [19..19] DBG_TMR6_STOP                                                    */
      __IOM uint32_t DBG_TMR7_STOP : 1;         /*!< [20..20] DBG_TMR7_STOP                                                    */
      __IOM uint32_t DBG_CAN2_STOP : 1;         /*!< [21..21] DBG_CAN2_STOP                                                    */
    } CR_B;
  } ;
} DBG_T;                                     /*!< Size = 8 (0x8)                                                            */



/** @} */ /* End of group Device_Peripheral_peripherals */

/** FMC base address in the alias region */
#define FMC_BASE            ((uint32_t)0x08000000)
/** SRAM base address in the alias region */
#define SRAM_BASE             ((uint32_t)0x20000000)
/** Peripheral base address in the alias region */
#define PERIPH_BASE           ((uint32_t)0x40000000)

/** SRAM base address in the bit-band region */
#define SRAM_BB_BASE          ((uint32_t)0x22000000)
/** Peripheral base address in the bit-band region */
#define PERIPH_BB_BASE        ((uint32_t)0x42000000)

/** FSMC registers base address */
#define FSMC_R_BASE           ((uint32_t)0xA0000000)

/** Peripheral memory map */
#define APB1PERIPH_BASE       PERIPH_BASE
#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

#define TMR2_BASE             (APB1PERIPH_BASE + 0x0000)
#define TMR3_BASE             (APB1PERIPH_BASE + 0x0400)
#define TMR4_BASE             (APB1PERIPH_BASE + 0x0800)
#define TMR5_BASE             (APB1PERIPH_BASE + 0x0C00)
#define TMR6_BASE             (APB1PERIPH_BASE + 0x1000)
#define TMR7_BASE             (APB1PERIPH_BASE + 0x1400)
#define TMR12_BASE            (APB1PERIPH_BASE + 0x1800)
#define TMR13_BASE            (APB1PERIPH_BASE + 0x1C00)
#define TMR14_BASE            (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
#define WWDT_BASE             (APB1PERIPH_BASE + 0x2C00)
#define IWDT_BASE             (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
#define BAKR_BASE              (APB1PERIPH_BASE + 0x6C00)
#define PMU_BASE              (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)

#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
#define EINT_BASE             (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
#define TMR1_BASE             (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
#define TMR8_BASE             (APB2PERIPH_BASE + 0x3400)
#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
#define TMR15_BASE            (APB2PERIPH_BASE + 0x4000)
#define TMR16_BASE            (APB2PERIPH_BASE + 0x4400)
#define TMR17_BASE            (APB2PERIPH_BASE + 0x4800)
#define TMR9_BASE             (APB2PERIPH_BASE + 0x4C00)
#define TMR10_BASE            (APB2PERIPH_BASE + 0x5000)
#define TMR11_BASE            (APB2PERIPH_BASE + 0x5400)

#define SDIO_BASE             (PERIPH_BASE + 0x18000)

#define DMA1_BASE              (AHBPERIPH_BASE + 0x0000)
#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

#define DMA2_BASE              (AHBPERIPH_BASE + 0x0400)
#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

#define RCM_BASE               (AHBPERIPH_BASE + 0x1000)
#define CRC_BASE               (AHBPERIPH_BASE + 0x3000)

/** Flash registers base address */
#define FMC_R_BASE          (AHBPERIPH_BASE + 0x2000)
/** Flash Option Bytes base address */
#define OB_BASE               ((uint32_t)0x1FFFF800)

#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
#define ETH_MAC_BASE          (ETH_BASE)
#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
#define ETH_DMA_BASE          (ETH_BASE + 0x1000)

/** FSMC Bank1 registers base address */
#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
/** FSMC Bank1E registers base address */
#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
/** FSMC Bank2 registers base address */
#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
/** FSMC Bank3 registers base address */
#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
/**FSMC Bank4 registers base address  */
#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)

/** Debug MCU registers base address */
#define DBGMCU_BASE          ((uint32_t)0xE0042000)

#define USART2              ((USART_T *)USART2_BASE)
#define USART3              ((USART_T *)USART3_BASE)
#define UART4               ((USART_T *)UART4_BASE)
#define UART5               ((USART_T *)UART5_BASE)
#define AFIO                ((AFIO_T *)AFIO_BASE)
#define GPIOA               ((GPIO_T *)GPIOA_BASE)
#define GPIOB               ((GPIO_T *)GPIOB_BASE)
#define GPIOC               ((GPIO_T *)GPIOC_BASE)
#define GPIOD               ((GPIO_T *)GPIOD_BASE)
#define GPIOE               ((GPIO_T *)GPIOE_BASE)
#define GPIOF               ((GPIO_T *)GPIOF_BASE)
#define GPIOG               ((GPIO_T *)GPIOG_BASE)
#define USART1              ((USART_T *)USART1_BASE)
#define RCM                 ((RCM_T *)RCM_BASE)
#define FMC                 ((FMC_T *)FMC_R_BASE)
#define FSMC                ((FSMC_T*)FSMC_R_BASE)
#define PMU                 ((PMU_T*)PMU_BASE)
#define EINT                ((EINT_T*)EINT_BASE)
#define DMA1                ((DMA1_T*)DMA1_BASE)
#define DMA2                ((DMA1_T*)DMA2_BASE)
#define SDIO                ((SDIO_T*)SDIO_BASE)
#define RTC                 ((RTC_T*)RTC_BASE)
#define BAKR                ((BAKR_T*)BAKR_BASE)
#define IWDT                ((IWDT_T*)IWDT_BASE)
#define WWDT                ((WWDT_T*)WWDT_BASE)
#define TMR1                ((TMR_T*)TMR1_BASE)
#define TMR8                ((TMR_T*)TMR8_BASE)
#define TMR2                ((TMR_T*)TMR2_BASE)
#define TMR3                ((TMR_T*)TMR3_BASE)
#define TMR4                ((TMR_T*)TMR4_BASE)
#define TMR5                ((TMR_T*)TMR5_BASE)
#define TMR9                ((TMR_T*)TMR9_BASE)
#define TMR12               ((TMR_T*)TMR12_BASE)
#define TMR10               ((TMR_T*)TMR10_BASE)
#define TMR11               ((TMR_T*)TMR11_BASE)
#define TMR13               ((TMR_T*)TMR13_BASE)
#define TMR14               ((TMR_T*)TMR14_BASE)
#define TMR15               ((TMR_T *)TMR15_BASE)
#define TMR16               ((TMR_T *)TMR16_BASE)
#define TMR17               ((TMR_T *)TMR17_BASE)
#define TMR6                ((TMR_T*)TMR6_BASE)
#define TMR7                ((TMR_T*)TMR7_BASE)
#define I2C1                ((I2C_T*)I2C1_BASE)
#define I2C2                ((I2C_T*)I2C2_BASE)
#define SPI1                ((SPI_T*)SPI1_BASE)
#define SPI2                ((SPI_T*)SPI2_BASE)
#define SPI3                ((SPI_T*)SPI3_BASE)
#define ADC1                ((ADC_T*)ADC1_BASE)
#define ADC2                ((ADC_T*)ADC2_BASE)
#define ADC3                ((ADC_T*)ADC3_BASE)
#define CAN1                ((CAN_T*)CAN1_BASE)
#define CAN2                ((CAN_T*)CAN2_BASE)
#define DAC                 ((DAC_T*)DAC_BASE)
#define DBG                 ((DBG_T*)DBGMCU_BASE)
#define CRC                 ((CRC_T*)CRC_BASE)
#define OB                  ((OB_T *) OB_BASE)

#define DMA1_Channel1        ((DMA_Channel_T *) DMA1_Channel1_BASE)
#define DMA1_Channel2        ((DMA_Channel_T *) DMA1_Channel2_BASE)
#define DMA1_Channel3        ((DMA_Channel_T *) DMA1_Channel3_BASE)
#define DMA1_Channel4        ((DMA_Channel_T *) DMA1_Channel4_BASE)
#define DMA1_Channel5        ((DMA_Channel_T *) DMA1_Channel5_BASE)
#define DMA1_Channel6        ((DMA_Channel_T *) DMA1_Channel6_BASE)
#define DMA1_Channel7        ((DMA_Channel_T *) DMA1_Channel7_BASE)

#define DMA2_Channel1        ((DMA_Channel_T *) DMA2_Channel1_BASE)
#define DMA2_Channel2        ((DMA_Channel_T *) DMA2_Channel2_BASE)
#define DMA2_Channel3        ((DMA_Channel_T *) DMA2_Channel3_BASE)
#define DMA2_Channel4        ((DMA_Channel_T *) DMA2_Channel4_BASE)
#define DMA2_Channel5        ((DMA_Channel_T *) DMA2_Channel5_BASE)


/* Define one bit mask */
#define BIT0    0x00000001
#define BIT1    0x00000002
#define BIT2    0x00000004
#define BIT3    0x00000008
#define BIT4    0x00000010
#define BIT5    0x00000020
#define BIT6    0x00000040
#define BIT7    0x00000080
#define BIT8    0x00000100
#define BIT9    0x00000200
#define BIT10   0x00000400
#define BIT11   0x00000800
#define BIT12   0x00001000
#define BIT13   0x00002000
#define BIT14   0x00004000
#define BIT15   0x00008000
#define BIT16   0x00010000
#define BIT17   0x00020000
#define BIT18   0x00040000
#define BIT19   0x00080000
#define BIT20   0x00100000
#define BIT21   0x00200000
#define BIT22   0x00400000
#define BIT23   0x00800000
#define BIT24   0x01000000
#define BIT25   0x02000000
#define BIT26   0x04000000
#define BIT27   0x08000000
#define BIT28   0x10000000
#define BIT29   0x20000000
#define BIT30   0x40000000
#define BIT31   0x80000000

/**
  * @}
  */

 /**
  * @}
  */ 
#ifdef USE_STDPERIPH_DRIVER
  #include "apm32f10x_conf.h"
#endif
/** @addtogroup Exported_macro
  * @{
  */
#define SET_BIT(REG, BIT)     ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))

#define READ_BIT(REG, BIT)    ((REG) & (BIT))

#define CLEAR_REG(REG)        ((REG) = (0x0))

#define WRITE_REG(REG, VAL)   ((REG) = (VAL))

#define READ_REG(REG)         ((REG))

#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __APM32F10x_H */

